We present a voltage mode switched-capacitor fieldprogrammableanalogarray (FPAA) to be used to implement various analog circuits. The FPAA consists of uniform configurable analog blocks (CABs) allowing implementati...
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We present a voltage mode switched-capacitor fieldprogrammableanalogarray (FPAA) to be used to implement various analog circuits. The FPAA consists of uniform configurable analog blocks (CABs) allowing implementation of different functions. Each CAB consists of two back-to-back connected inverting and noninverting strays-insensitive switched-capacitor integrators. The interconnection between CABs is implemented by switched and unswitched capacitor networks. The internal structure of CABs and the interconnection between different CABs are configured by user-programmable digital control signals. The functionality of the FPAA is demonstrated through embedding of different types of filters, programmable amplifiers, biquads, modulators and signal generators along with simulation results.
This paper presents a new approach to develop fieldprogrammableanalogarrays (FPAAs),(1) which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also intro...
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This paper presents a new approach to develop fieldprogrammableanalogarrays (FPAAs),(1) which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.
This paper presents a probabilistic-based design methodology for a random number generator according to any given probability density function. Our basic idea is to perform massively parallel analog computation throug...
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ISBN:
(纸本)9781509001545
This paper presents a probabilistic-based design methodology for a random number generator according to any given probability density function. Our basic idea is to perform massively parallel analog computation through Gaussian mixture modelling. There are two main contributions in this work. First, we developed a new approach to performing Gaussian mixture decomposition with simple analog circuits. Second, we have presented a novel methodology to exploit the stochastic switching behavior of Magnetic Tunneling Junction (MTJ) as a hardware-efficient Gaussian noise generator. Our resulting universal random number generator not only achieves extremely low energy consumption and ultra-high computing performance, but also is highly reconfigurable. Consequently, it can be widely applicable in many hardware-based signal processing applications, especially quite useful in the newly emerging stochastic-based computing systems. Finally, to validate our design, we used field-programmable analog array to implement all required components.
This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connectio...
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This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.
This paper presents a probabilistic-based design methodology for a random number generator according to any given probability density function. Our basic idea is to perform massively parallel analog computation throug...
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ISBN:
(纸本)9781509001552
This paper presents a probabilistic-based design methodology for a random number generator according to any given probability density function. Our basic idea is to perform massively parallel analog computation through Gaussian mixture modelling. There are two main contributions in this work. First, we developed a new approach to performing Gaussian mixture decomposition with simple analog circuits. Second, we have presented a novel methodology to exploit the stochastic switching behavior of Magnetic Tunneling Junction (MTJ) as a hardware-efficient Gaussian noise generator. Our resulting universal random number generator not only achieves extremely low energy consumption and ultra-high computing performance, but also is highly reconfigurable. Consequently, it can be widely applicable in many hardware-based signal processing applications, especially quite useful in the newly emerging stochastic-based computing systems. Finally, to validate our design, we used field-programmable analog array to implement all required components.
The limited power budgets of sensor networks necessitate some level of in-network pre-processing to reduce communication overhead. The low power consumption of analog signal processing (ASP) is well-suited for this ta...
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ISBN:
(纸本)9781450319591
The limited power budgets of sensor networks necessitate some level of in-network pre-processing to reduce communication overhead. The low power consumption of analog signal processing (ASP) is well-suited for this task. However, the quick adoption of this technology has been restrained by the fact that ASP implementation requires a priori knowledge of the application space. Our solution to this challenge is to enable run-time reconfiguration through the use of a field-programmable analog array (FPAA). In the same way that reconfigurable digital systems allow system designers to change the infrastructure of digital blocks, an FPAA allows an application developer to change the infrastructure of, and even tune, ASP blocks without circuit-level expertise. We will demonstrate that an FPAA can be used to (1) facilitate the use of ASP to reduce power consumption, and to (2) allow run-time reconfigurability to maximize ASP impact.
A theoretical study of the behavior of some elementary first- and second-order functions, which are suitable for realizing negative group delay, is performed in this work. As both the gain and phase responses are simu...
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A theoretical study of the behavior of some elementary first- and second-order functions, which are suitable for realizing negative group delay, is performed in this work. As both the gain and phase responses are simultaneously considered, important derivations related to the actual bandwidth of operation are derived accompanied by useful design tips. The presented theory is supported by simulation and experimental results obtained through the utilization of typical active-RC filter structures, as well as from a field-programmable analog array device.
In this work, we propose an alternative for the circuital realization of analog fractional-order differentiators and integrators without using ladder networks. This alternative is obtained by a mathematical manipulati...
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In this work, we propose an alternative for the circuital realization of analog fractional-order differentiators and integrators without using ladder networks. This alternative is obtained by a mathematical manipulation of a rational function in a similar way to the reported for the synthesis of the variable-state filters. The advantage of the proposed implementation is the requirement of only simple analog design blocks, such as integrators (of integer order), differential amplifiers and two-input adder amplifiers. Most important, contrarily to other reported solutions, the proposed realization can be fulfilled using commercially available resistors and capacitors, with a reduced number of calculations, and without negative impedance converters or inductors. In addition, the orders of the fractional derivative and integral can be modified just varying the gain of the differential amplifiers and adders. To validate the proposal of implementation, and as example of application, we present simulations (HSPICE, MATLAB) and experimental results of a first-order plus dead time plant controlled by fractional-order PI and PID controllers. The experimental results were obtained from a realization using field-programmable analog arrays. A comparison analysis highlights that the proposed alternative of implementation presents advantages regarding a Cauer-network-based realization in terms of number of active and passive elements, number of passive elements with non-commercial available values and design complexity.
While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. fieldprogrammableanalogarrays (FPAAs) built with trans...
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While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. fieldprogrammableanalogarrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. An FPAA built using Multiple Input Translinear Elements (MITEs) has been designed, fabricated in 0.35 mu m CMOS, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, RMS-to-DC converters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.
This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurab...
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This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR40.42 dB, 2D-DCT processor with PSNR53.05 dB and RGB-to-YCrCb converter with PSNR46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.
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