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27th IEEE Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Glick, Dallon Grigg, Jesse Nelson, Brent Wirthlin, Michael Brigham Young Univ Dept Elect & Comp Engn NSF Ctr Space High Performance & Resilient Comp S Provo UT 84602 USA

ISBN: (纸本)9781728111315

This paper presents Maverick, a proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target partial reconfiguration (PR) regions in field-programmable gate array (FPGA) designs. After an initial static design and PR region are created with Xilinx's Vivado PR flow, the Maverick flow can then compile and configure RMs onto that PR region-without the use of vendor tools. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. This paper describes the Maverick flow and shows the results of it running on a PYNQ-Z1's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

关键词： field-programmable gate arrays Partial reconfiguration Electronic design automation and methodology RapidSmith

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Real-Time State Estimation and Voltage Stability Assessment of Power Grids: From Theoretical Foundations to Practical Applications

Real-Time State Estimation and Voltage Stability Assessment ...

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作者： Andreas Martin KETTNER ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE

学位级别：博士

The operators of power distribution systems strive to lower their operational costs and improve the quality of the power service provided to their customers. Furthermore, they are faced with the challenge of accommodating large numbers of Distributed Energy Resources (DERs) into their grids. It is expected that these problems will be tackled with a large-scale deployment of automation technology, which will enable the real-time monitoring and control of power distribution systems (i. e., similar to power transmission systems). For this purpose, real-time situation awareness w. r. t. the state and the stability of the system is needed. In view of the deployment of such automation functions into power distribution grids, there are two binding requirements. Firstly, the system models have to account for the inherent unbalances of power distribution systems (i. e., w. r. t. the components of the grid and the loads). Secondly, the analysis methods have to be real-time capable when deployed into low-cost embedded systems platforms, which are the cornerstones of automation. In other words, the analysis methods need to be computationally efficient. This thesis focuses on the modeling of unbalanced polyphase power systems, as well as the development, validation, and deployment of real-time methods for State Estimation (SE) and Voltage Stability Assessment (VSA) for such systems. More precisely, the following theoretical and practical contributions are made to the field of power system engineering. 1. Fundamental properties of the compound admittance matrix of polyphase power grids are identified. Specifically, theorems w. r. t. the rank of the compound admittance matrix, the feasibility of Kron Reduction (KR), and the existence of compound hybrid matrices are stated and formally proven. These theorems hold for generic polyphase power grids (i. e., which may be unbalanced, and have an arbitrary number of phases). 2. A Voltage Stability Index (VSI) for real-time VSA of polypha

关键词： power distribution systems automation active distribution networks microgrids polyphase power systems unbalanced power grids compound admittance matrix compound hybrid matrix Kron reduction state estimation sequential Kalman filter phasor measurement units voltage stability assessment voltage stability index L -index Thevenin equivalent polynomial load model embedded systems field-programmable gate arrays COMMELEC

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A RRAM-based FPGA for energy-efficient edge computing 20

A RRAM-based FPGA for energy-efficient edge computing

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Proceedings of the 23rd Conference on Design, Automation and Test in Europe

作者： Xifan Tang Edouard Giacomin Patsy Cadareanu Ganesh Gore Pierre-Emmanuel Gaillardon University of Utah

ISBN: (纸本)9783981926347

The shift from centralized cloud to edge computing demands hardware systems with data processing capability at ultra-low power. Reconfigurable solutions such as field-programmable gate arrays (FPGAs) offer a high flexibility in terms of hardware implementation and are thus popular for use in many edge computing systems. However, breaking through the energy wall of FPGAs is a challenge, as low-power operation often requires compromising performances. In this paper, we study a low-power high-performance FPGA architecture exploiting Resistive Random Access Memory (RRAM) technology. To perform a comprehensive analysis, we introduce a novel design flow which can rapidly prototype FPGA fabrics from which accurate area, delay, and power results can be obtained. Based on full-chip layouts and SPICE simulations, we show that RRAM-based FPGAs can improve up to 8%/22%/16% in area/delay/power compared to SRAM-based counterparts at nominal voltage. Even when operated at a near-Vt supply, the proposed RRAM-based FPGA can improve the Energy-Delay Product by about 2 X without any delay overhead, when compared to an SRAM-based FPGA. In addition, Monte Carlo simulations showed that the proposed RRAM-based FPGA architecture stays robust under different CMOS process corners as well as under a 30% RRAM resistance standard deviation.

关键词： low-power design field-programmable gate arrays resistive memories

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FPGA-Based Architecture for Medium Access Techniques in Broadband PLC

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IEEE ACCESS 2018年 6卷 9534-9542页

作者： Poudereux, Pablo Hernandez, Alvaro Cruz-Roldan, Fernando Mateos, Raul Univ Alcala Dept Elect E-28805 Alcala De Henares Spain Univ Alcala Signal Theory & Commun Dept E-28805 Alcala De Henares Spain

In this paper, two real-time architectures of medium access techniques useful for future generation of wireline and wireless communication systems are presented. One architecture is based on discrete cosine transform (DCT), while the second approach implements a filter-bank multi-carrier (FBMC) system. A comparative analysis, in terms of resource consumption, performance, and precision, is shown. The comparison considers a floating-point model, a fixed-point model, and experimental tests. These models make it possible to evaluate the effect of the fixed-point precision in the implementation and, in turn, to verify the correctness of the developed architecture. The simulation models and the experimental tests have been carried out in different practical environments in order to achieve a further analysis. The two proposed architectures have been implemented on a field-programmable gate array (FPGA) device. Furthermore, the architectures have been included as advanced peripherals in a system-on-chip, which also integrates a soft microprocessor to monitor the whole system and manage the data transfers. As a communication scenario, the proposed architectures have been particularized to operate in real time while meeting all timing requirements de fined by a broadband power line communications standard. For that case, the system has achieved a desired transmission rate of 62.5 Ms/s at the converters, providing mean squared errors, at the output for an ideal channel, below 3 .10(-5) for both the DCT and FBMC approaches, whereas each transmitter/receiver requires around 50% of the DSP cells available in the Xilinx XC6VLX240T FPGA, the most demanded resource in the device.

关键词： field-programmable gate arrays multi-carrier communication (MCM) filter-bank multicarrier (FBMC) systems broadband power-line communications discrete cosine transform (DCT)

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Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2018年第11期37卷 5127-5142页

作者： Joseph, Georgina Binoy Devanathan, R. Toc H Inst Sci & Technol Dept Elect & Commun Engn Kochi Kerala India Hindustan Inst Technol & Sci Sch Elect Engn Madras Tamil Nadu India

Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing pipelining at digit level. Multiplierless constant coefficient multiplication using the shift-and-add technique is widely used in digital signal processing applications. This paper proposes a novel bit serial adaptation of the parallel shift-and-add algorithm to online arithmetic. The proposed multipliers use right shifts instead of the traditional left shifts resulting in causal online implementations. Graph-based and hybrid algorithms are developed for the estimation of the distance of a constant from a set of constants in terms of the number of additions and for the synthesis of online multiple constant multipliers under area and online delay constraints. The computational complexity of the algorithms is determined. Results of implementation on randomly generated constant sets and FIR filter instances show substantial improvements in the number of operations required using the distance heuristic. Further, it is shown that the proposed techniques and algorithms result in significant savings in resource utilization, logic depth, and clock frequency compared to parallel and digit-serial algorithms.

关键词： Online arithmetic Digital signal processing Constant coefficient multiplication Graph-based algorithms field-programmable gate arrays

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Onboard Processing With Hybrid and Reconfigurable Computing on Small Satellites

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PROCEEDINGS OF THE IEEE 2018年第3期106卷 458-470页

作者： George, Alan D. Wilson, Christopher M. Univ Pittsburgh Dept Elect & Comp Engn Dept NSF Ctr Space High Performance & Resilient Comp Pittsburgh PA 15261 USA Univ Pittsburgh NSF Ctr Space High Performance & Resilient Comp Pittsburgh PA 15261 USA

Due to the increasing demands of onboard sensor and autonomous processing, one of the principal needs and challenges for future spacecraft is onboard computing. Space computers must provide high performance and reliability (which are often at odds), using limited resources (power, size, weight, and cost), in an extremely harsh environment (due to radiation, temperature, vacuum, and vibration). As spacecraft shrink in size, while assuming a growing role for science and defense missions, the challenges for space computing become particularly acute. For example, processing capabilities on CubeSats (smaller class of SmallSats) have been extremely limited to date, often featuring microcontrollers with performance and reliability barely sufficient to operate the vehicle let alone support various sensor and autonomous applications. This article surveys the challenges and opportunities of onboard computers for small satellites (SmallSats) and focuses upon new concepts, methods, and technologies that are revolutionizing their capabilities, in terms of two guiding themes: hybrid computing and reconfigurable computing. These innovations are of particular need and value to CubeSats and other SmallSats. With new technologies, such as CHREC Space Processor (CSP), we demonstrate how system designers can exploit hybrid and reconfigurable computing on SmallSats to harness these advantages for a variety of purposes, and we highlight several recent missions by NASA and industry that feature these principles and technologies.

关键词： Fault-tolerant systems field-programmable gate arrays radiation effects reconfigurable architectures satellites space radiation

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A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第7期65卷 2196-2209页

作者： Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Data Storage Networks & Proc DSN Lab Tehran 111558639 Iran Sharif Univ Technol Dept Comp Engn Tehran 111558639 Iran

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in field-programmable gate arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance overhead to these blocks. In addition, we present an efficient scheme to load the configuration bitstream into the memory elements, which makes the configuration time comparable to that of SRAM-based FPGAs. Besides, we investigate the correct functionality and reliability of the programming structure subject to fluctuations in attributes of RRAM cells. Using Versatile Place and Route (VTR) tool with the obtained characteristics of the proposed blocks demonstrate that the average area and delay of the proposed FPGA architecture are 59.4% and 20.1% less than conventional SRAM-based FPGAs. Compared with a recent RRAM-based architecture, the proposed architecture improves the area and power by 49.7% and 33.8% while keeps the delay intact.

关键词： Emerging non-volatile memory resistive random access memory field-programmable gate arrays programming circuitry resistive fluctuation

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Real-Time Finite-Element Simulation of Electromagnetic Transients of Transformer on FPGA

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IEEE TRANSACTIONS ON POWER DELIVERY 2018年第4期33卷 1991-2001页

作者： Liu, Peng Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2R3 Canada

The computation of the electromagnetic transients in a power transformer with nonlinear material using the finite element method (FEM) is so dense that the traditional nonlinear solver employing the Newton-Raphson method can hardly execute in real time. In this paper, we emulate the finite-element computation of electromagnetic transients of a transformer in real time for the first time. The transmission line modeling (TLM) method employed in the FEM successfully decoupled the nonlinear elements from the linear network so the nonlinearities could he solved individually, which is perfect for parallel processing. The parallelism of the TLM-FE solution is sufficiently explored and realized on a field-programmable gate array with deep data pipelining, and the implementation can execute in real time and provide detailed field information of the transformer during the transients. The proposed noniterative field-circuit coupling enabled the transformer to interface with an external network and the comparison with commercial FEM software proved the accuracy and computational efficiency of the real-time FE model.

关键词： Electromagnetic transients field-programmable gate arrays field-circuit coupling finite element method parallel processing power transformer real-time systems transmission line modeling

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Enhanced Model and Real-Time Simulation Architecture for Modular Multilevel Converter

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IEEE TRANSACTIONS ON POWER DELIVERY 2018年第1期33卷 466-476页

作者： Ashourloo, Mojtaba Mirzahosseini, Ramin Iravani, Reza Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

This paper presents i) an equivalent model of the half-bridge modular multilevel converter (HB-MMC) which is suitable for real-time applications, ii) a hybrid central-processing unit/ field-programmable gate array (CPU/FPGA)-based architecture for real-time simulation of electromagnetic transients of systems which include HB-MMC, and iii) a novel arrangement for sorting results referred to as the "sub-module (SM) rank list", which tackles the bottleneck for parallel implementation of the MMC arm model solver on the FPGA. The Adam-Bashforth (AB) method is used for numerical integration of the HB-SM capacitor model. The second-order AB method provides a constant admittance matrix of the HB-MMC and, thus, reduces computational burden while offering the same accuracy as that of the widely used Trapezoidal method. The CPU/FPGA-based architecture is optimized to obtain maximum parallelism of the HB-MMC model implementation, adopting a standard, single-precision, floating-point computational engine. The proposed sorting arrangement is independent of the utilized sorting algorithm and its application to the odd-even bubble sorting scheme is presented in this paper. The proposed architecture offers a simulation time-step of 825 ns while including the sorting module as the SM capacitor voltage-balancing control unit. This enables accurate analysis of MMC controls based on either software-in-the-loop or hardware-in-the-loop approaches. Performance and accuracy of the MMC model and the hybrid CPU/FPGA-based architecture are evaluated based on a set of case studies on a 401-level HB-MMC-based HVDC station and verified based on offline simulation results in the PSCAD/EMTDC environment.

关键词： Equivalent circuits field-programmable gate arrays HVDC converters real-time systems

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Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL

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ALGORITHMS 2019年第8期12卷 149-149页

作者： Faict, Thomas D'Hollander, Erik H. Goossens, Bart Univ Ghent Dept Elect & Informat Syst B-9052 Ghent Belgium Univ Ghent IMEC IPI Dept Telecommun & Informat Proc B-9000 Ghent Belgium

Intel recently introduced the Heterogeneous Architecture Research Platform, HARP. In this platform, the Central Processing Unit and a field-programmable gate Array are connected through a high-bandwidth, low-latency interconnect and both share DRAM memory. For this platform, Open Computing Language (OpenCL), a High-Level Synthesis (HLS) language, is made available. By making use of HLS, a faster design cycle can be achieved compared to programming in a traditional hardware description language. This, however, comes at the cost of having less control over the hardware implementation. We will investigate how OpenCL can be applied to implement a real-time guided image filter on the HARP platform. In the first phase, the performance-critical parameters of the OpenCL programming model are defined using several specialized benchmarks. In a second phase, the guided image filter algorithm is implemented using the insights gained in the first phase. Both a floating-point and a fixed-point implementation were developed for this algorithm, based on a sliding window implementation. This resulted in a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance of 430 GOPS and a throughput of HD color images at 74 frames per second.

关键词： field-programmable gate arrays OpenCL high-performance computing guided image filter

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