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A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation

IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS 2018年第4期4卷 533-547页

作者： Yu, Ye Jha, Niraj K. Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

The exponentially increasing performance of chip multiprocessors (CMPs) predicted by Moore's Law is no longer due to the increasing clock rate of a single CPU core, but on account of the increase of core counts in the CMP. More transistors are integrated within the same footprint area as the technology node shrinks to deliver higher performance. However, this is accompanied by higher power dissipation that usually exceeds the coping capability of inexpensive cooling techniques. This Power Wall prevents the chip from running at full speed with all the devices powered-on. This is known as the dark silicon problem. Another major bottleneck in CMP development is the imbalance between the CPU clock rate and memory access speed. This Memory Wall keeps the CPU from fully utilizing its compute power. To address both the Power and Memory Walls, we propose a monolithic 3D hybrid architecture that consists of a multi-core CPU tier, a fine-grain dynamically reconfigurable (FDR) field-programmable gate array (FPGA) tier, and multiple resistive RAM (RRAM) tiers. The FDR tier is used as an accelerator. It uses the concept of temporal logic folding to localize on-chip communication. The RRAM tiers are connected to the CPU and FDR tiers through an efficient memory interface that takes advantage of the tremendous bandwidth available from monolithic inter-tier vias and hides the latency of large data transfers. We evaluate the architecture on two types of benchmarks: compute-intensive and memory-intensive. We show that the architecture reduces both power and energy significantly at a better performance for both types of applications. Compared to the baseline, our architecture achieves an average of 43.1x and 2.5x speedup on compute-intensive and memory-intensive benchmarks, respectively. The power and energy consumption are reduced by 5.0x and 40.5x, respectively, for compute-intensive applications, and 2.0x and 4.2x, respectively, for memory-intensive applications. This translates to

关键词： Dynamic reconfiguration field-programmable gate arrays hybrid architecture monolithic 3D integration memory-processor interface

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Implementation and optimisation of pulse compression algorithm on open CL-based FPGA

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JOURNAL OF ENGINEERING-JOE 2019年第21期2019卷 7752-7754页

作者： Feng, Yingxu Hu, Shanqing Li, Xingming Yu, Jiacheng Beijing Inst Technol Sch Informat & Elect Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China Beijing Sci & Technol Leike Elect Informat Techno Beijing 10081 Peoples R China

As Moore's law meets bottlenecks, the demand for heterogeneous parallel processing systems is increasing. field-programmable gate arrays (FPGAs) are becoming more efficient acceleration devices due to their powerful processing performance, and the CPU + FPGA architecture under the OpenCL framework has become the trend of heterogeneous parallel processing systems. This study focuses on the optimisation of pulse compression algorithm in FPGA based on OpenCL, which plays an important role in modern radar signal processing systems. By using double cache for ping-pang storage of data between matched filter and inverse fast Fourier transform (IFFT), an optimised processing method is proposed by using a pipeline and verify the method by using Arria 10 GX1150 FPGA with two groups of 2 GB DDR3;the results show that the proposed method can achieve 2.89x performance improvement over the conventional implementation.

关键词： optimisation field programmable gate arrays pulse compression matched filters cache storage fast Fourier transforms microprocessor chips inverse transforms parallel architectures OpenCL framework heterogeneous parallel processing systems pulse compression algorithm optimised processing method Arria 10 GX1150 FPGA open CL-based FPGA Moore's law field-programmable gate arrays efficient acceleration devices processing performance CPU-FPGA architecture radar signal processing systems double cache ping-pang storage DDR3 matched filter IFFT storage capacity 2 Gbit

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Learning accelerator of deep neural networks with logarithmic quantization 7

Learning accelerator of deep neural networks with logarithmi...

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7th IIAI International Congress on Advanced Applied Informatics (IIAI-AAI)

作者： Ueki, Takeo Iwai, Keisuke Matsubara, Takashi Kurokawa, Takakazu Natl Def Acad Japan Dept Comp Sci Yokosuka Kanagawa Japan

ISBN: (纸本)9781538674475

In recent years, Deep Neural Network (DNN)s have become widely spread. Several high-throughput hardware implementations for DNNs have been proposed. One of the key points for hardware implementations of DNNs is to reduce their circuit scale because DNNs require a lot of product-sum operations. Previous papers presented some accelerators using logarithmic quantization to reduce circuit scale by replacing multipliers with shifters. However, most of them are implemented only for inference, and we can find no previous paper using logarithmic quantization for learning. In this paper, a learning accelerator using a logarithmic quantization is proposed. The accelerator uses a stochastic approach for logarithmic quantization. It enables DNNs to learn using logarithmic quantization values. Preliminary evaluation confirmed that DNNs using the proposed method can achieve recognition of MNIST with an accuracy of 97.8%. This evaluation result proves that the proposed method can be used for learning DNNs. The accelerator using the proposed method is implemented on a field-programmable gate array (FPGA) (Xilinx Zynq7020) and synthesized with Xilinx Vivado 2017.1. As a result, it is confirmed to have 2.9 times smaller circuit scale compared with the same FPGA accelerator using 32-bit fixed point number.

关键词： neural networks logarithmic computation approximate computing field-programmable gate arrays

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Implementing Propositional Networks on FPGA 31th

Implementing Propositional Networks on FPGA

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31st Australasian Joint Conference on Artificial Intelligence (AI)

作者： Siwek, Cezary Kowalski, Jakub Sironi, Chiara F. Winands, Mark H. M. Univ Wroclaw Fac Math & Comp Sci Inst Comp Sci Wroclaw Poland Maastricht Univ Dept Data Sci & Knowledge Engn Games & AI Grp Maastricht Netherlands

ISBN: (纸本)9783030039912;9783030039905

The speed of game rules processing plays an essential role in the performance of a General Game Playing (GGP) agent. Propositional Networks (propnets) are an example of a highly efficient representation of game rules. So far, in GGP, only software implementations of propnets have been proposed and investigated. In this paper, we present the first implementation of propnets on field-programmable gate arrays (FPGAs), showing that they perform between 25 and 58 times faster than a software-propnet for most of the tested games. We also integrate the FPGA-propnet within an MCTS agent, discussing the challenges of the process, and possible solutions for the identified shortcomings.

关键词： General Game Playing field-programmable gate arrays Propositional Networks Monte Carlo Tree Search

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Burst-Mode FEC Performance for PON Upstream Channels with EDFA Optical Transients 22

Burst-Mode FEC Performance for PON Upstream Channels with ED...

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International Conference on Optical Network Design and Modeling (ONDM)

作者： Brandonisio, Nicola Carey, Daniel Porto, Stefano Talli, Giuseppe Townsend, Paul D. Univ Coll Tyndall Natl Inst Cork Ireland

ISBN: (纸本)9783903176072

The performance of forward error correction (FEC) based on Reed-Solomon coding is analyzed experimentally for a burst-mode upstream channel within a passive optical network (PON) testbed. During this analysis, the upstream FEC performance is impaired by inducing correlated and localized errors within the burst through the injection of optical transients. These transients emulate the optical signal variation associated with the add-and-drop events of wavelength channels within a long-reach optical link based on a chain of erbium doped fiber amplifiers (EDFAs). The robustness of the FEC has been analyzed by measuring the post-FEC bit error rate (BER) as a function of the amplitude of the emulated transients and their delay with respect to the transmitted bursts. A margin of approximately 4dB is demonstrated for the transient amplitude before the FEC degradation. Furthermore, while the post-FEC BER is strongly degraded by the emulated transients, the pre-FEC BER stays below the FEC threshold, demonstrating the importance of measuring the post-FEC BER in order to correctly characterize the FEC performance in PON upstream channels affected by optical transients.

关键词： forward error correction passive optical networks burst-mode transmission field-programmable gate arrays erbium doped fiber amplifiers optical transients

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FPGA-based Real-Time Super-Resolution System for Ultra High Definition Videos 26

FPGA-based Real-Time Super-Resolution System for Ultra High ...

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26th IEEE Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： He, Zhuolun Huang, Hanxian Jiang, Ming Bai, Yuanchao Luo, Guojie Peking Univ Ctr Energy Efficient Comp & Applicat Beijing 100871 Peoples R China Peking Univ Sch Math Sci Dept Informat Sci Beijing 100871 Peoples R China Peking Univ Sch Elect Engn & Comp Sci Beijing 100871 Peoples R China

ISBN: (纸本)9781538655221

The market benefits from a barrage of Ultra High Definition (Ultra-HD) displays, yet most extant cameras are barely equipped with Full-HD video capturing. In order to upgrade existing videos without extra storage costs, we propose an FPGA-based super-resolution system that enables real-time Ultra-HD upscaling in high quality. Our super-resolution system crops each frame into blocks, measures their total variation values, and dispatches them accordingly to a neural network or an interpolation module for upscaling. This approach balances the FPGA resource utilization, the attainable frame rate, and the image quality. Evaluations demonstrate that the proposed system achieves superior performance in both throughput and reconstruction quality, comparing to current approaches.

关键词： field-programmable gate arrays Ultra High Definition Super-Resolution Real-time

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AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive Applications 37

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

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37th IEEE International Performance Computing and Communications Conference (IPCCC)

作者： Jadhav, Shrikant S. Gloster, Clay Doss, Christopher Kim, Youngsoo Naher, Jannatun North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27401 USA North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC USA Bradley Univ Dept Elect & Comp Engn Peoria IL 61625 USA

ISBN: (纸本)9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. The user needs only provide the VHDL description of a special-purpose floating point Arithmetic Logic Unit (ALU) or function core. The tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. The multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. The multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. The Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable Computing field-programmable gate arrays field-programmable Custom Computing Machines High Performance Computing Multi-Memory Architecture Multiple Memory Banks

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Real Time Photon-Counting Receiver for High Photon Efficiency Optical Communications

Real Time Photon-Counting Receiver for High Photon Efficienc...

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作者： Vyhnalek, Brian E.(NASA Glenn Research Center, Cleveland, OH, United States) Nappier, Jennifer M.(NASA Glenn Research Center, Cleveland, OH, United States) Tedder, Sarah A.(NASA Glenn Research Center, Cleveland, OH, United States) IEEE International Conference on Space Optical Systems and Applications October 14 2019 - October 16 2019 Portland OR United States

We present a scalable design for a photon-counting ground receiver based on superconducting nanowire single photon detectors (SNSPDs) and field programmable gate array (FPGA) real-time processing for applications to space-to-ground photon starved links, such as the Orion EM-2 Optical Communication Demonstration (O2O), and future deep space or low transmitter power missions. The receiver is designed to receive a serially concatenated pulse position modulation (SCPPM) waveform, which follows the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization Red Book standard. The receiver design uses multiple individually fiber coupled, 80% detection efficiency commercial SNSPDs in parallel to scale to a required data rate, and is capable of achieving data rates up to 528 Mbps. For efficient fiber coupling from the telescope to the array of parallel detectors that can be scaled both to telescope aperture size and the number of detectors, we use either a single mode fiber (SMF) photonic lantern or a few-mode fiber (FMF) photonic lantern. In this paper we give an overview of the receiver system design, the characteristics of the photonic lanterns, the performance of the SNSPDs, and system level tests. We show that 40 Mbps can be received using a single SNSPD, and discuss aspects for scaling to higher data rates.

关键词： Aerospace systems Cost effectiveness Real time operation Space communication Superconductivity Systems engineering Transmitter receivers Cryogenic temperature Deep space Design analysis Extremely high frequencies Fiber optics field-programmable gate arrays Optical communication Photons

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Can DSP48A1 Adders be used for High-Resolution Delay Generation? 7

Can DSP48A1 Adders be used for High-Resolution Delay Generat...

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7th Mediterranean Conference on Embedded Computing (MECO)

作者： Tancock, Scott Arabul, Ekin Dahnoun, Naim Mehmood, Shahid Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Quaid I Azam Univ Islamabad Pakistan

ISBN: (纸本)9781538656839

Time to digital conversion is an important task in many systems. It involves the conversion of time-based signals (as opposed to the amplitude-based signals in analog-to-digital conversion) into digital numbers so that a purely digital system may process them. This is widely used in rangefinders, all-digital phase-locked loops and quantum experiments. In order to obtain high-resolution time-to-digital conversion, the generation of small delays is necessary. This paper examines the viability of using the DSP48A1 blocks present on Xilinx FPGAs to generate these small delays, and ultimately concludes they are unsuitable in isolation due to the high differential non-linearity, but may be suitable as a semi-fine stage of a multi-stage TDC or when combined in an equivalent coding line.

关键词： Time-to-Digital Converters field-programmable gate arrays Xilinx Digital Signal Processing Delay Generation

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Towards Compilation of an Imperative Language for FPGAs 10

Towards Compilation of an Imperative Language for FPGAs

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10th ACM SIGPLAN International Workshop on Virtual Machines and Language Implementations (VMIL)

作者： Pauget, Baptiste Pearce, David J. Potanin, Alex Ecole Normale Super Dept Informat Paris France Victoria Univ Wellington Engn & Comp Sci Wellington New Zealand

ISBN: (纸本)9781450360715

field-programmable gate arrays (FPGA's) have been around since the early 1980s and have now achieved relatively widespread use. For example, FPGAs are routinely used for high-performance computing, financial applications, seismic modelling, DNA sequence alignment, software defined networking and, occasionally, are even found in smartphones. And yet, despite their success, there still remains something of a gap between programming languages and circuit designs for an FPGA. We consider the compilation of an imperative programming language, Whiley, to VHDL for use on an FPGA. A key challenge lies in splitting an arbitrary function into a series of pipeline stages, as necessary to expose as much task parallelism as possible. To do this, we introduce a language construct which gives the programmer control over how the pipeline is constructed.

关键词： field-programmable gate arrays Compilers Hardware Description Languages

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