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作者： Lantz, N. C Nappier, J. M Vyhnalek, B. E Tedder, S. A NASA Glenn Research Center International Society for Optical Engineering

A unique challenge in the development of a deep space optical software defined radio (SDR) transmitter is the optimization of the extinction ratio (ER). For a Mars to Earth optical link, an ER approaching 40dB may be necessary. However, a high ER can be difficult to achieve at the low PPM orders and narrow slot widths required for high data rates. The quality of the digital signal transmitted by the SDR does not meet the amplitude and timing characteristics needed by an analog optical modulator. The conflicting implementation constraints of these two fundamentally different systems, the digital SDR and analog optical modulator, can make achieving the required ER very difficult. In this paper, the causes of fidelity loss at the interface between the SDR and optical modulator are discussed. The SDR signal quality requirements are derived and explored. It is shown that increasing the SDR signal quality enough to meet these requirements is impractical to implement due to bandwidth limitations of electronic components as well as field programmable gate Array (FPGA) clock speed constraints. A novel optical modulation architecture based on low-voltage differential signaling and dual Mach-Zehnder modulators is presented which reduces the signal quality requirements on the SDR and increases the system ER.

关键词： Bandwidth Deep space field-programmable gate arrays Modulators Optical communication Pulse position modulation Radio transmitters

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Impact of Initialization on gate-based Area Efficient Ternary Content-Addressable Memory 1

Impact of Initialization on Gate-based Area Efficient Ternar...

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1st IEEE International Conference on Computing, Electronics and Communications Engineering (iCCECE)

作者： Irfan, Muhammad Ahmad, Aftab CECOS Univ IT & Emerging Sci Dept Elect Engn Peshawar Pakistan Univ Sci & Technol Dept Elect Engn Bannu Pakistan

ISBN: (纸本)9781538649046

Ternary content-addressable memory gives an address at the output after searching for the word that is provided at the input. The word ternary means that the said memory is capable of storing 'X' which represents the presence of '1' as well as '0'. gate-based area efficient TCAM (G-AETCAM) uses flip-flops as storing media in the form of storing as well as masking element. These flip-flops are millions in number in the latest FPGA devices and are used only 1% in implementing G-AETCAM of size 64x36. In this paper, we have initialized the flip-flops to some binary value ('1' or '0'). Technically, these flip-flops are made SET when we want to initialize it by '1' and are made CLEAR if we need to store '0' in the corresponding storing or masking element. The said algorithm of initialization is implemented successfully on Xilinx Virtex-6 FPGA for 64 x 36 configuration which resulted in 3.45% decrease in power consumption and 0.83% increase in speed of the whole architecture.

关键词： Flip-flops field-programmable gate arrays memory content-addressable storage ternary content-addressable storage

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Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2017年第2期13卷 397-414页

作者： Ratnayake, Kumara Amer, Aishy Concordia Univ Dept Elect & Comp Engn Montreal PQ Canada

Video processing algorithms are computationally intensive and place stringent requirements on performance and efficiency of memory bandwidth and capacity. As such, efficient hardware accelerations are inevitable for fast video processing systems. In this paper, we propose resource- and power-optimized FPGA-based configurable architecture for video object detection by integrating noise estimation, Mixture-of-Gaussian background modeling, motion detection, and thresholding. Due to large amount of background modeling parameters, we propose a novel Gaussian parameter compression technique suitable for resource- and power-constraint embedded video systems. The proposed architecture is simulated, synthesized and verified for its functionality, accuracy and performance on a Virtex-5 FPGA-based embedded platform by directly interfacing to a digital video input. Intentional exploitation of heterogeneous resources in FPGAs, and advanced design techniques such as heavy pipelining and data parallelism yield real-time processing of HD-1080p video streams at 30 frames per second. Objective and subjective evaluations to existing hardware-based methods show that the proposed architecture obtains orders of magnitude performance improvements, while utilizing minimal hardware resources. This work is an early attempt to devise a complete video surveillance system onto a stand-alone resource-constraint FPGA-based smart camera.

关键词： field-programmable gate arrays FPGA Video signal processing Noise Moving objects Motion detection Thresholding Gaussian background update Gaussian parameter compression

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PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

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IEEE TRANSACTIONS ON COMPUTERS 2017年第6期66卷 982-995页

作者： Ebrahimi, Zahra Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Tehran *** Iran

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in field-programmable gate arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of Reconfigurable Hard Logics (RHLs) and a small-input LUT. In the proposed architecture, we selectively turn off unused RHLs and/or LUTs within each logic block by employing a reconfigurable controller. By mapping a majority of logic functions to simple-design RHLs, PEAF is able to significantly improve power efficiency without deteriorating the performance. Experimental results over a comprehensive set of benchmarks (MCNC, IWLS'05, and VTR) demonstrate that compared with baseline four-LUT architecture, PEAF reduces the total static power and Power-Delay-Product (PDP), on average, by 24.5 and 21.7 percent, respectively. This is while the overall system performance is also improved by 1.8 percent. PEAF increases total area by 18.9 percent, however, it still occupies 22.1 percent less area footprint than the six-LUT architecture with 31.5 percent improvement in PDP.

关键词： field-programmable gate arrays static power SRAM dark silicon hard logic

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System-Level, FPGA-Based, Real-Time Simulation of Ship Power Systems

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IEEE TRANSACTIONS ON ENERGY CONVERSION 2017年第2期32卷 737-747页

作者： Milton, Matthew Benigni, Andrea Bakos, Jason Univ South Carolina Dept Elect Engn Columbia SC 29208 USA Univ South Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

In this paper, we present a scalable approach for real-time simulation of ship power systems with high-frequency power electronics converters (100-200 kHz). The proposed approach is based on the latency-based linear multistep compound method and relies on field-programmable gate array (FPGA) execution. Several examples of increasing dimension and complexity are used to evaluate the scalability-both of in terms of computational delay and of resources usage-of the proposed approach. Real-time execution with a 50 ns time step is achieved for all the examples considered.

关键词： field-programmable gate arrays parallel algorithms power system simulation power electronics real time systems

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An efficient systolic array grid-based structure of the robust Bayesian regularization technique for real-time enhanced imaging in uncertain remote sensing environment

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2017年第4期13卷 783-796页

作者： Castillo Atoche, A. Carrasco Alvarez, R. Palma Marrufo, O. Vazquez Castillo, J. Univ Autonoma Yucatan Dept Mechatron Ave Ind Contaminantes S-N Perifer Norte Merida Yucatan Mexico Univ Guadalajara Elect Engn Div Blvd Marcelino Garcia Barragan 1421 Guadalajara Jalisco Mexico Univ Quintana Roo Div Sci Blvd Bahia S-N Esq Ignacio Comonfort Chetmal Quintana Roo Mexico

In this paper, we address a hardware implementation of the efficient robust Bayesian regularization architecture for the real-time enhancement of large-scale remote sensing (RS) imaging. The efficient sense of the proposed architecture is related to the high-performance embedded implementation that is achieved with the aggregation of parallel computing and systolic array design techniques in a novel grid connected-based accelerator. Then, the developed high-speed accelerator is integrated with an embedded processor via the HW/SW co-design paradigm. The presented approach is used for solving RS image enhancement/reconstruction of the ill-conditioned inverse spatial spectrum pattern estimation problems via an interesting low-cost high-performance embedded computing solution. Finally, we show the achieved results and how we drastically reduced the computational load for real-world large-scale geospatial images.

关键词： Remote sensing Real-time systems Systolic array architectures field-programmable gate arrays

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CUTE Mote, A Customizable and Trustable End-Device for the Internet of Things

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IEEE SENSORS JOURNAL 2017年第20期17卷 6816-6824页

作者： Gomes, Tiago Salgado, Filipe Tavares, Adriano Cabral, Jorge Univ Minho Ctr ALGORITMI P-4800058 Guimaraes Portugal

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks' architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing-and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices.

关键词： Accelerator architectures heterogeneous networks Internet of Things field-programmable gate arrays wireless sensor networks

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G-AETCAM: gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA

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IEEE ACCESS 2017年 5卷 20785-20790页

作者： Irfan, Muhammad Ullah, Zahid CECOS Univ IT & Emerging Sci Dept Elect Engn Peshawar 25100 Pakistan

This paper presents a novel architecture for ternary content-addressable memory (TCAM), using G-AETCAM cells, which outputs the address of the provided input data. The proposed architecture is a matrix of G-AETCAM cells arranged in the form of rows and columns using flip-flop as a memory element and a control logic circuitry consisting of logic gates. One G-AETCAM cell encodes the input and stored bit into one encoded bit which results in a match-line after passing from the AND-gate-array. Many architectures configure random-access memory (RAM) available on FPGAs as content-addressable storage architecture but are efficient for specific size and deal with data only in ascending or descending order while the proposed architecture provides freedom in size with no chance of making a single memory cell as useless and can store ternary data in any order. RAM-based TCAMs require pre-processing for the storage of TCAM words while the proposed design does not involve any pre-processing. The proposed architecture reduces the transistor count by a factor of 25.55, as compared with the RAM-based TCAM, which ultimately reduces area and increases the speed of operations. The proposed architecture is successfully implemented on Xilinx Virtex-6 FPGA for the size 64 x 36 and achieves a speed of 358 MHz.

关键词： Content-addressable storage field-programmable gate arrays flip-flops logic gates memory RAM-based TCAM

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A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2017年第11期28卷 3033-3045页

作者： Elrabaa, Muhammad E. S. Hroub, Ayman Mudawar, Muhamed F. Al-Aghbari, Amran Al-Asli, Mohammed Khayyat, Ahmad King Fahd Univ Petr & Minerals Comp Engn Dept Dhahran 31261 Saudi Arabia

Simulation is the main tool for computer architects and parallel application developers for developing new architectures and parallel algorithms on many-core machines. Simulating a many-core architecture represent a challenge to software simulators even with parallelization of these SW on multi-cores. field programmable gate arrays offer an excellent implementation platform due to inherent parallelism. Existing FPGA-based simulators however, are mostly execution-driven which consumes too many FPGA resources. Hence, they still trade-off accuracy with simulation speed as SW simulators do. In this work, an application-level trace-driven FPGA-based many-core simulator is presented. A parameterized Verilog template was developed that can generate any number of simulator tiles. The input trace has an architecturally agnostic format that is directly interpreted by the FPGA-based timing model to re-construct the execution events of the original application with accurate timing. This allows fitting a large number of simulation tiles on a single FPGA without sacrificing simulation speed or accuracy. Experimental results show that the simulator's average accuracy is similar to 14 percent with simulation speeds ranging from 100's of MIPs to over 2,200 MIPS for a 16-core target architecture. Hence, with accuracy similar to SW simulators, its speed is higher than all other FPGA-based simulators.

关键词： Trace-driven simulations hardware simulators chip-multiprocessors multithreading field-programmable gate arrays

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Optimization and performance evaluation of graphic processing units for voice processing

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JOURNAL OF ALGORITHMS & COMPUTATIONAL TECHNOLOGY 2017年第4期11卷 388-394页

作者： Sayadi, Fatma E. Bahri, Haythem Chouchene, Marwa Atri, Mohamed Monastir Univ Fac Sci Lab Elect & Microelect EE Environm St Monastir 5019 Tunisia

With the advancement in the device technology and parallel architecture, field-programmable gate arrays (FPGAs) can well perform the speech processing operation. FPGAs have very impressive results, despite their low operating frequency, by completely extracting the parallelism. Nevertheless, recent central processing unit and graphic processing unit (GPU) have also an inherent feature for high performance. In fact, recent GPUs enable dramatic increases in computing performance by harnessing great number of cores. In this context, we seek to analyze the performance of the linear prediction coding algorithm implementation on two different platforms: one based on the GPU NVIDIA GeForce GTX 480 and another on the FPGA Spartan-6. Subsequently, we try to apply several optimization strategies on those platforms. The experimental results highlight the relative robustness or weakness of both these platforms. The tests prove that, for several samples, GPU manages speedups of up to 4x compared to the FPGA and around 48x compared to a sequential execution.

关键词： Linear predictive coding graphic processing unit field-programmable gate arrays optimization strategies shared memory

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