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NASA Technical Reports Server (Ntrs) 20120004266: Florida Tech Cubesat Experiment Feasibility Study

2016年

NASA Technical Reports Server (Ntrs) 20120004266: Florida Tech Cubesat Experiment Feasibility Study by NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20120004266: accelerometers arrasmith, william w. controllers cubesat electrical engineering experiment feasibility feasibility analysis field-programmable gate arrays low earth orbits nasa technical reports server (ntrs) payloads picosatellites platt, don requirements risk management spaceborne experiments superhigh frequencies technology assessment vibration tests

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NASA Technical Reports Server (Ntrs) 20110016388: Absolute Position Encoders with Vertical Image Binning

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2016年

NASA Technical Reports Server (Ntrs) 20110016388: Absolute Position Encoders with Vertical Image Binning by NASA Technical Reports Server (Ntrs); NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20110016388: absolute binning charge coupled devices coders encoders field-programmable gate arrays high speed image classification image processing imaging techniques leviton, douglas b. nasa technical reports server (ntrs) optoelectronic devices pattern recognition pixels rates (per time) readout sequencing signal analyzers

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NASA Technical Reports Server (Ntrs) 20150000446: Aeroflex Technology as Class-Y Demonstrator

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2016年

NASA Technical Reports Server (Ntrs) 20150000446: Aeroflex Technology as Class-Y Demonstrator by NASA Technical Reports Server (Ntrs); NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20150000446: aeroflex agarwal, shri chips (electronics) class-y demonstrator electronic equipment tests electronic packaging field-programmable gate arrays nasa technical reports server (ntrs) popelar, scott reliability analysis solders stress analysis suh, jong-ook technology assessment

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NASA Technical Reports Server (Ntrs) 20150015964: Single Event Effects in Fpga Devices 2014-2015

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2016年

NASA Technical Reports Server (Ntrs) 20150015964: Single Event Effects in Fpga Devices 2014-2015 by NASA Technical Reports Server (Ntrs); NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20150015964: accelerated life tests berg, melanie d. devices domains effects embedding field-programmable gate arrays ion beams label, kenneth a. latch-up nasa technical reports server (ntrs) pellish, jonathan redundancy single event upsets

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NASA Technical Reports Server (Ntrs) 20140000672: Physics of Failure Analysis of Xilinx Flip Chip Ccga Packages: Effects of Mission Environments on Properties of LP2 Underfill and Ati Lid Adhesive Materials

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2016年

NASA Technical Reports Server (Ntrs) 20140000672: Physics of Failure Analysis of Xilinx Flip Chip Ccga Packages: Effects of Mission Environments on Properties of LP2 Underfill and Ati Lid Adhesive Materials by NASA Te... 详细信息

关键词： (ntrs) 20140000672: adhesive adhesives aerospace environments analysis effects failure analysis field-programmable gate arrays nasa technical reports server (ntrs) reliability suh, jong-ook technology utilization

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NASA Technical Reports Server (Ntrs) 20140017350: Xilinx Virtex-5Qv (V5Qv) Independent Seu Data

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2016年

NASA Technical Reports Server (Ntrs) 20140017350: Xilinx Virtex-5Qv (V5Qv) Independent Seu Data by NASA Technical Reports Server (Ntrs); NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) (v5qv) 20140017350: berg, melanie d. circuits electronic equipment tests field-programmable gate arrays independent label, kenneth a. nasa technical reports server (ntrs) pellish, jonathan performance tests radiation damage radiation tolerance reports single event upsets

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Acceleration of EM-Based 3D CT Reconstruction Using FPGA

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2016年第3期10卷 754-767页

作者： Choi, Young-kyu Cong, Jason Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

Reducing radiation doses is one of the key concerns in computed tomography (CT) based 3D reconstruction. Although iterative methods such as the expectation maximization (EM) algorithm can be used to address this issue, applying this algorithm to practice is difficult due to the long execution time. Our goal is to decrease this long execution time to an order of a few minutes, so that low-dose 3D reconstruction can be performed even in time-critical events. In this paper we introduce a novel parallel scheme that takes advantage of numerous block RAMs on field-programmable gate arrays (FPGAs). Also, an external memory bandwidth reduction strategy is presented to reuse both the sinogram and the voxel intensity. Moreover, a customized processing engine based on the FPGA is presented to increase overall throughput while reducing the logic consumption. Finally, a hardware and software flow is proposed to quickly construct a design for various CT machines. The complete reconstruction system is implemented on an FPGA-based server-class node. Experiments on actual patient data show that a 26.9 speedup can be achieved over a 16-thread multicore CPU implementation.

关键词： Accelerator architectures computed tomography field-programmable gate arrays parallel architectures ray tracing

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FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2015年第10期23卷 1987-2000页

作者： Lin, Ting-Jung Zhang, Wei Jha, Niraj K. Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the areadelay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations;2) diagonal direct links are incorporated to improve the flexibility of local communication;and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by 3.6x compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective areadelay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.

关键词： Dynamic reconfiguration field-programmable gate arrays integrated circuits logic folding

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Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2015年第11期23卷 2531-2539页

作者： Licciardo, Gian Domenico D'Arienzo, Antonio Rubino, Alfredo Univ Salerno Dept Ind Engn I-84084 Salerno Italy

In this paper, an architecture design of a hardware accelerator capable to expand the dynamic range of low dynamic range images to the 32-bit high dynamic range counterpart is presented. The processor implements on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to elaborate a full-HD (1920 x 1080 pixels) image in 16.6 ms (60 frames/s) on field-programmable logic (FPL), by processing the incoming pixels in streaming order, without frame buffers. In this way, the design avoids the use of external DRAM and can be tightly coupled with acquiring devices, thus to enable the implementation of smart sensors. The processor complexity can be configured with different area/speed ratios to meet the requirements of different target platforms from FPLs to ASICs, obtaining, in both implementations, state-of-the-art performances.

关键词： Dynamic range field-programmable gate arrays image processing integrated circuits inverse tone mapping (iTM)

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Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2015年第2期64卷 453-465页

作者： Shreejith, Shanker Fahmy, Suhaib A. Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore TUM CREATE Singapore 138602 Singapore

Modern vehicles incorporate an increasing number of distributed compute nodes, resulting in the need for faster and more reliable in-vehicle networks. Time-triggered protocols such as FlexRay have been gaining ground as the standard for high-speed reliable communications in the automotive industry, marking a shift away from the event-triggered medium access used in controller area networks (CANs). These new standards enable the higher levels of determinism and reliability demanded from next-generation safety-critical applications. Advanced applications can benefit from tight coupling of the embedded computing units with the communication interface, thereby providing functionality beyond the FlexRay standard. Such an approach is highly suited to implementation on reconfigurable architectures. This paper describes a field-programmable gate array (FPGA)-based communication controller (CC) that features configurable extensions to provide functionality that is unavailable with standard implementations or off-the-shelf devices. It is implemented and verified on a Xilinx Spartan 6 FPGA, integrated with both a logic-based hardware ECU and a fully fledged processor-based electronic control unit (ECU). Results show that the platform-centric implementation generates a highly efficient core in terms of power, performance, and resource utilization. We demonstrate that the flexible extensions help enable advanced applications that integrate features such as fault tolerance, timeliness, and security, with practical case studies. This tight integration between the controller, computational functions, and flexible extensions on the controller enables enhancements that open the door for exciting applications in future vehicles.

关键词： Automotive systems field-programmable gate arrays networks

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