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IEEE 27th International Conference on Data Engineering (ICDE 2011)

作者： Woods, Louis Teubner, Jens Alonso, Gustavo Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (纸本)9781424489589

We demonstrate a hardware implementation of a complex event processor, built on top of field-programmable gate arrays (FPGAs). Compared to CPU-based commodity systems, our solution shows distinctive advantages for stream monitoring tasks, e.g., wire-speed processing and predictable performance. The demonstration is based on a query-to-hardware compiler for complex event patterns that we presented at VLDB 2010 [1]. By example of a click stream monitoring application, we illustrate the inner workings of our compiler and indicate how FPGAs can act as efficient and reliable processors for event streams.

关键词： Automata CPU-based commodity systems Decoding Event detection FPGA field programmable gate arrays Hardware Monitoring Pattern matching VLDB 2010 click stream monitoring application complex event patterns complex event processor field programmable gate arrays field-programmable gate arrays file servers microprocessor chips pattern matching predictable performance program processors query-to-hardware compiler real-time pattern matching wire-speed processing

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Analysis of Within-Die Process Variation in 65nm FPGAs

Analysis of Within-Die Process Variation in 65nm FPGAs

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International Symposium on Quality Electronic Design

作者： Tim Tuan Austin Lesea Chris Kingsley Steve Trimberger Xilinx Research Labs

ISBN: (纸本)9781612849133

FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use densely distributed test oscillators to measure within-die performance variation across a large sample of dies, and identify both random and spatially correlated systematic components through post-processing. Finally, we evaluate the benefit of modeling within-die systematic variation in static timing analysis.

关键词： field-programmable gate arrays Within-die variation Systematic variation Variation-aware design

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Conversion Algorithms and Implementations for Koblitz Curve Cryptography

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IEEE TRANSACTIONS ON COMPUTERS 2010年第1期59卷 81-92页

作者： Brumley, Billy Bob Jarvinen, Kimmo U. Aalto Univ Dept Informat & Comp Sci Espoo 02150 Finland

In this paper, we discuss conversions between integers and tau-adic expansions and we provide efficient algorithms and hardware architectures for these conversions. The results have significance in elliptic curve cryptography using Koblitz curves, a family of elliptic curves offering faster computation than general elliptic curves. However, in order to enable these faster computations, scalars need to be reduced and represented using a special base-tau expansion. Hence, efficient conversion algorithms and implementations are necessary. Existing conversion algorithms require several complicated operations, such as multiprecision multiplications and computations with large rationals, resulting in slow and large implementations in hardware and microcontrollers with limited instruction sets. Our algorithms are designed to utilize only simple operations, such as additions and shifts, which are easily implementable on practically all platforms. We demonstrate the practicability of the new algorithms by implementing them on Altera Stratix II FPGAs. The implementations considerably improve both computation speed and required area compared to the existing solutions.

关键词： Elliptic curve cryptography Koblitz curves field-programmable gate arrays public-key cryptosystems

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An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2010年第6期59卷 1663-1670页

作者： Szplet, Ryszard Klepacki, Kamil Mil Univ Technol PL-00908 Warsaw Poland

We present the design and test results of a new time-to-digital converter based on the cyclic pulse shrinking method and implemented in a field-programmable gate array (FPGA) device. The pulse shrinking is realized in a loop containing two complementary delay lines. The first line shrinks, and the second line stretches the duration time of a circulating pulse;hence, the length ratio of the lines determines the pulse-shrinking capability of the converter. This resolution control mechanism is different from the bias adjustment typically used in complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) pulse-shrinking elements. Two forms of representation of a measured time interval (the pulse width and the time interval between two pulses) are utilized in the described converter to improve the efficiency of resolution control. To diminish the jitter of the edges of a circulating pulse and, consequently, to increase the precision of the converter, a two-stage conversion is introduced. The first stage, having a low resolution, rapidly shortens the measured pulse, thus limiting the number of cycles, whereas the second stage provides a final high resolution within a narrow time interval range. The optimal resolution of the first conversion stage is theoretically derived. Mostly, the same logical resources of the FPGA device are utilized in both conversion stages;thus, the overall area overhead of the converter is reduced. The converter has a resolution of 42 ps and a measurement uncertainty of below 56 ps within the measurement range of 11.5 ns. The converter has been implemented in a general-purpose reprogrammable device Spartan-3 (Xilinx).

关键词： field-programmable gate arrays pulse shrinking time digitizer time-to-digital converter two-stage interpolation

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MATRIX STRUCTURES AND PARALLEL ALGORITHMS FOR IMAGE SUPERRESOLUTION RECONSTRUCTION

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SIAM JOURNAL ON MATRIX ANALYSIS AND APPLICATIONS 2010年第4期31卷 1873-1893页

作者： Zhang, Qiang Guy, Richard T. Plemmons, Robert J. Wake Forest Univ Hlth Sci Dept Biostat Sci Winston Salem NC 27159 USA Wake Forest Univ Dept Math Winston Salem NC 27109 USA Wake Forest Univ Dept Math & Comp Sci Winston Salem NC 27109 USA

Computational resolution enhancement (superresolution) is generally regarded as a memory-intensive process due to the large matrix-vector calculations involved. In this paper, a detailed study of the structure of the n(2) x n(2) superresolution matrix is used to decompose the matrix into nine matrices of size l(2) x l(2), where l is the upsampling factor. As a result, previously large matrix-vector products can be broken into many small, parallelizable products. An algorithm is presented that utilizes the structural results to perform superresolution on compact, highly parallel architectures such as field-programmable gate arrays.

关键词： image superresolution field-programmable gate arrays parallel computation structured matrices

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High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines

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IEEE TRANSACTIONS ON NEURAL NETWORKS 2010年第11期21卷 1780-1792页

作者： Le Ly, Daniel Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 x 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

关键词： Boltzmann machines computer architecture field-programmable gate arrays neural network hardware parallel processing

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FPGA Power Reduction by Guarded Evaluation 10

FPGA Power Reduction by Guarded Evaluation

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18th ACM International Symposium on field-programmable gate arrays

作者： Anderson, Jason H. Ravishankar, Chirag Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs;in this paper, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering "non-inverting paths" in the circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by 22%, on average, and can reduce power consumption in the FPGA interconnect by 14%.

关键词： field-programmable gate arrays FPGAs power optimization low-power design logic synthesis technology mapping

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A Less Configuration Memory Reconfigurable Logic Device with Error Detect and Correct Circuit

A Less Configuration Memory Reconfigurable Logic Device with...

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IEEE Region 10 Conference on TENCON 2010

作者： Zhao, Qian Ichinomiya, Yoshihiro Okamoto, Yasuhiro Amagasaki, Motoki Iida, Masahiro Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol Kumamoto 8608555 Japan

ISBN: (纸本)9781424468904

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

关键词： EDC circuit Hamming code based error detect Hamming codes configuration memory reconfigurable logic device correct circuit error detect circuit field-programmable gate arrays logic circuits reconfigurable architectures reconfigurable logic element table l

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Power-aware FPGA Routing Fabrics and Design Tools

Power-aware FPGA Routing Fabrics and Design Tools

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18th IEEE/IFIP International Conference on VLSI and System-on-Chip

作者： Nishida, Shoichi Eto, Jyunya Amagasaki, Motoki Iida, Masahiro Kuga, Morihiro Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol Kumamoto 8608555 Japan

ISBN: (纸本)9781424464708

The performance of field-programmable gate arrays (FPGAs) has been significantly improved due to a new process technology. However, several problems have arisen in the new generation FPGAs. Specifically, the issue of power consumption is a serious issue, because FPGAs have many routing resources. We report on the improvement of both the FPGA routing structure and electronic design automation (EDA) tools in order to solve this issue. In order to reduce the power consumption, high activity nets are assigned to low load lines, which is the routing structure used for small-world networks in FPGAs. In addition, the clustering and routing algorithms of the EDA tools are improved to complement the routing structure. This report demonstrates that the power can be reduced. Based on evaluation results, a maximum power consumption improvement of 48.4% was obtained, and the average improvement was 22.9% when using the proposed routing structure and EDA tools.

关键词： clustering algorithms electronic design automation electronic design automation tools field programmable gate arrays field-programmable gate arrays network routing power consumption power-aware FPGA routing fabrics

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A SCALABILITY STUDY OF FRACTIONAL MOTION ESTIMATION FOR H.264 ENCODING

A SCALABILITY STUDY OF FRACTIONAL MOTION ESTIMATION FOR H.26...

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23rd Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Vasiljevic, Jasmina Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada

ISBN: (纸本)9781424453771

Fractional motion estimation (FME) is an important part of the H.264/AVC video encoding standard. The algorithm can significantly increase the compression ratio of video encoders while at the same time improve video quality. The FME algorithm, however, is also computationally expensive and can consist of over 45% of the total motion estimation process. To maximize the performance and efficiency of the FME implementations on field-programmable gate arrays (FPGAs), one needs to effectively exploit the inherent parallelism in the algorithm. In this work, we define two scalability approaches in order to intelligently parallelize the computing hardware. We implemented five scaled FME designs on a Xilinx XC5VLX330T (Virtex-5) FPGA. We found that scaling vertically with an 4x4 subblock is more efficient than scaling horizontally across several subblocks. It is shown that the best vertically scaled design can achieve 128 fps when encoding full 1920x1088 progressive HDTV video with only 20.7K LUTS and 23.4K registers.

关键词： Fractional Motion Estimation H.264/AVC field-programmable gate arrays

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