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12th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Jadhav, Shrikant S. Gloster, Clay Naher, Jannatun Doss, Christopher Kim, Youngsoo San Jose State Univ San Jose CA 95192 USA North Carolina A&T State Univ Greensboro NC USA Bradley Univ Peoria IL 61625 USA

ISBN: (纸本)9781665406901

In this paper, we present an FPGA-based multi-memory controller for accelerating computationally intensive applications. Our architecture accepts multiple inputs and produces multiple outputs for each clock cycle. The architecture includes processor cores with pipelined functional units tailored for each application. Additionally, we present an approach to achieve one to two orders-of-magnitude speedup over a traditional software implementation executing on a conventional multi-core processor. Even though the clock frequency of the field-programmable Custom Computing Machine (FCCM) is an order-of-magnitude slower than a conventional multi-core processor, the FCCM is significantly faster. We used the Power function as an application to demonstrate the merits of our FCCM. In our experiments, we executed the Power function in software and compared the software execution times with the execution time of an FCCM. Additionally, we also compared FCCM execution time with the OpenMP implementation of the function. Our experiments show that the results obtained using our multi-memory architecture are 57X faster than software implementation and 17X faster than OpenMP implementation executing the Power function, respectively.

关键词： Reconfigurable Computing field-programmable gate arrays field-programmable Custom Computing Machines High Performance Computing Multi-Memory Architecture Multiple Memory Banks

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A parallel and pipelined implementation of a pascal-simplex based multi-asset option pricer on FPGA using OpenCL

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MICROPROCESSORS AND MICROSYSTEMS 2022年 90卷 1页

作者： Mahony, Aidan O. Zeidan, Gil Hanzon, Bernard Popovici, Emanuel Univ Coll Cork Dept Elect & Elect Engn Cork Ireland Intel Corp Programmable Solut Grp Houston TX USA Univ Coll Cork Dept Math Cork Ireland

Multi-asset option pricing is a financial tool that offers a competitive advantage in the global financial markets. To achieve the commercial advantage, performance and accuracy are two key desiderata of such tools. Techniques for financial option pricing have been actively researched for some time. Combined with recent advances in heterogeneous computing, new computing methods of lower latency option pricing have become available. field-programmable gate Array technology offers a powerful framework for building architectures for highly parallel option pricing. This paper presents a versatile, high performance implementation of an accurate multi-asset option pricer on an Intel Stratix 10 GX device. The implementation is highly flexible for the number of assets supported, the maximum tree depth, and the pipelining parameters. The theory that this architecture is based on is that of a recombining multinomial tree approach, which is a generalization of the binomial tree model. This novel architecture was implemented on field-programmable gate Array technology. The implementation presented in this paper enables the computation of an option price on up to 7 assets and can compute up to 43 times faster than a software implementation in a general-purpose processor.

关键词： Multi-asset option pricing field-programmable gate arrays Parameterized design OpenCL European options Hardware accelerators for finance

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Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2022年第4期27卷 34-34页

作者： Wang, Zi Schafer, Benjamin Carrion Univ Texas Dallas 800 W Campbell Rd Richardson TX 75083 USA

The quest to democratize the use of field-programmable gate arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes as input an untimed behavioral description and generates efficient RTL (Verilog or VHDL). One major advantage of HLS is that it allows us to generate a variety of different micro-architectures from the same behavioral description by simply specifying different combination of synthesis options. In particular, commercial HLS tools make extensive use of synthesize directives in the form pragmas. This strength is also a weakness as it forces HLS users to fully understand how these synthesis options work and how they interact to efficiently set them to get a hardware implementation with the desired characteristics. Luckily, this process can be automated. Unfortunately, the search space grows supra-linearly with the number of synthesis options. To address this, this work proposes an automatic synthesis option tuner dedicated for FPGAs. We have explored a larger number of behavioral descriptions targeting ASICs and FPGAs and found out that due to the internal structure of the FPGA a large number of synthesis options combinations never lead to a Pareto-optimal design and, hence, the search space can be drastically reduced. Moreover, we make use of large database of DSE results that we have generated since we started working in this field to further accelerate the exploration process. For this, we use a technique based on perceptual hashing that allows our proposed explorer to recognize similar program structures in the new description to be explored and match them with structures in our database. This allows us to directly retrieve the pragma settings that lead to Pareto-optimal configurations. Experimental results show that the search space can be accelerated substantially while leading to finding most of the Pareto-optim

关键词： High-level synthesis design space exploration field-programmable gate arrays

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A Survey of Recent Attacks and Mitigation on FPGA Systems 20

A Survey of Recent Attacks and Mitigation on FPGA Systems

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20th IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Duan, Shijin Wang, Wenhao Luo, Yukui Xu, Xiaolin Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

ISBN: (纸本)9781665439466

The emergence of a large variety of compute-intensive applications has made hardware accelerators a new necessity to deploy the corresponding high-complexity algorithms, such as the Deep Neural Network (DNN). Thanks to the flexibility from hardware reconfiguration and high power efficiency, field-programmable gate array (FPGA) has been widely utilized for building DNN hardware accelerators. In particular, FPGA has become one of the most popular edge platforms for deep-learning algorithm acceleration and machine learning as a service (MLaaS) in the cloud. Although significantly improving the performance of DNN algorithms, these FPGA-based accelerators also face unique and novel security vulnerabilities that the community should pay more attention to. This paper systematically reviews the state-ofthe-art research on FPGA-based hardware acceleration systems and their security issues, discusses the feasibility of existing defense solutions, and envisions future research directions.

关键词： Security field-programmable gate arrays

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Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale plus MPSoC 28

Implementation of Coprocessor for Integer Multiple Precision...

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28th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)

作者： Stefanski, Tomasz P. Rudnicki, Kamil Zebrowski, Wojciech Gdansk Univ Technol Fac Elect Telecommun & Informat Gdansk Poland Brightelligence Sp Zoo Dept Reconfigurable Syst Lodz Poland Aldec Inc Gdansk Off Gdansk Poland

ISBN: (纸本)9788363578190

Recently, we have opened the source code of coprocessor for multiple-precision arithmetic (MPA). In this contribution, the implementation and benchmarking results for this MPA coprocessor are presented on modern Zynq Ultrascale+ multi-processor system on chip, which combines field-programmable gate array with quad-core ARM Cortex-A53 64-bit central processing unit (CPU). In our benchmark, a single coprocessor can be up to 4.5 times faster than a single CPU core within the same chip emulating MPA using a software library.

关键词： field-programmable gate arrays fixed-point arithmetic scientific computing coprocessors digital circuits

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Implementation of DNNs on IoT devices

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NEURAL COMPUTING & APPLICATIONS 2020年第5期32卷 1327-1356页

作者： Zhang, Zhichao Kouzani, Abbas Z. Deakin Univ Sch Engn Geelong Vic 3216 Australia

Driven by the recent growth in the fields of internet of things (IoT) and deep neural networks (DNNs), DNN-powered IoT devices are expected to transform a variety of industrial applications. DNNs, however, involve many parameters and operations to process the data generated by IoT devices. This results in high data-processing latency and energy consumption. New approaches are thus being souhgt to tackle these issues and deploy real-time DNNs into resource-limited IoT devices. This paper presents a comprehensive review on hardware-and-software-co-design approaches developed to implement DNNs on low-resource hardware platforms. These approaches explore the trade-off between energy consumption, speed, classification accuracy, and model size. First, an overview of DNNs is given. Next, available tools for implementing DNNs on low-resource hardware platforms are described. Then, the memory hierarchy designs together with dataflow mapping strategies are presented. Furthermore, various model optimization approaches, including pruning and quantization, are discussed. In addition, case studies are given to demonstrate the feasibility of implementing DNNs for IoT applications. Finally, detailed discussions, research gaps, and future directions are provided. The presented review can guide the design and implementation of the next generation of hardware and software solutions for real-world IoT applications.

关键词： Deep neural networks Real-time accelerators Low-resource IoT devices Hardware and software co-design field-programmable gate arrays

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Modeling Method for Development of Digital System Algorithms Based on programmable Logic Devices

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CYBERNETICS AND SYSTEMS ANALYSIS 2020年第5期56卷 710-717页

作者： Letychevskyi, O. O. Peschanenko, V. S. Kharchenko, V. S. Volkov, V. A. Odarushchenko, O. M. Natl Acad Sci Ukraine VM Glushkov Inst Cybernet Kiev Ukraine Kherson State Univ Kherson Ukraine MM Zhukovsky Natl Aerosp Univ Kharkiv Aviat Inst Kharkiv Ukraine SPE RadiCS LLC Kropyvnytskyi Ukraine

The paper deals with state-of-the-art trends in the field of automated hardware development, specifically development of digital systems using programmable logic integrated circuits, as exemplified by field-programmable logic arrays. The paper suggests a modeling method of development using an algebraic model of design specifications, requirements and binary codes in order to apply formal methods of verification, model-based testing, as well as methods of algebraic matching. The specifications of the algebraic hardware model are behavior algebra determined on a set of actions and behaviors.

关键词： field-programmable gate arrays symbolic modeling algebraic matching behavior algebra

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High resolution FPGA pulse width modulation control of full-bridge DC-DC converters

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IET CIRCUITS DEVICES & SYSTEMS 2020年第7期14卷 1110-1116页

作者： Tomov, Viktor Iliev, Ivo Krasteva, Vessela Tech Univ Sofia Dept Elect Engn & Technol 8 Kl Ohridski BlvdBl 1 Sofia Bulgaria Bulgarian Acad Sci Inst Biophys & Biomed Engn Acad G Bonchev Str Bl 105 Sofia 1113 Bulgaria

This study describes a field-programmable gate arrays (FPGAs) based technique, which aims to significantly improve the resolution of complementary drivers in full-bridge DC-DC converters. An algorithm for precise adjustment of both the duty cycle and the frequency of the pulse width modulator (PWM) is presented. It is experimentally verified by software simulation and FPGA hardware implementation. The results prove that the designed 12-bit digital PWM is able to provide switching frequency of 100 kHz in the range of 99.61 [99.51-99.70] kHz [mean value (95% confidence interval)] using clock frequency of just 160 MHz. In comparison, the conventional counter-based PWM gives the same output resolution at operating frequency of 410 MHz. In addition, the proposed algorithm is scalable and could be used to provide better resolution even at higher clock frequencies >400 MHz. For example, if phase-locked loop is 480 MHz then the conventional counter for 100 kHz PWM has a resolution slightly >12 bits, while the proposed algorithm could extend the resolution up to 14 bits. Due to the high reliability of the FPGA technology, the proposed PWM control is applicable in highly critical medical systems, such as electrosurgical devices.

关键词： PWM power convertors DC-DC power convertors field programmable gate arrays driver circuits bridge circuits PWM control full-bridge DC-DC converters field-programmable gate arrays FPGA hardware implementation digital PWM switching frequency clock frequency counter-based PWM high resolution FPGA pulse width modulation control complementary drivers software simulation phase-locked loop electrosurgical devices frequency 100 0 kHz word length 12 0 bit word length 14 0 bit frequency 99 51 kHz to 99 70 kHz frequency 160 0 MHz to 480 MHz

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A Tag Based Random Order Vector Reduction Circuit

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IEEE ACCESS 2020年 8卷 41502-41515页

作者： Huang, Yihua Huang, Wenjin Chen, Rui Wu, Huangtao Wei, Ming Sun Yat Sen Univ Sch Elect & Informat Technol Guangzhou 510006 Peoples R China

Vector reduction is a very common operation to reduce a vector into a single scalar value in many scientific and engineering application scenarios. Therefore a fast and efficient vector reduction circuit has great significance to the real-time system applications. Usually the pipeline structure is widely adopted to increase the throughput of the vector reduction circuit and achieve maximum efficiency. In this paper, to deal with multiple vectors of variable length in random input sequence, a novel tag based fully pipelined vector reduction circuit is firstly proposed, in which a cache state module is used to queer and update the cache state of each vector. However, when the quantity of the input vector becomes large, a larger cache state module is required, which consumes more combinational logic and lower the operating frequency. To solve this problem, a high speed circuit is proposed in which the input vectors will be divided into several groups and sent into the dedicated cache state circuits, which can improve the operating frequency. Compared with other existing work, the prototype circuit and the improved circuit based on the prototype circuit can achieve the smallest Slices xus (<80% of the state-of-the-art work) for different input vector lengths. Moreover, both circuits can provide simple and efficient interface whose access timing is similar to that of a RAM. Therefore the circuits can be applied in a greater range.

关键词： Pipelines Hardware Clocks Adders field programmable gate arrays Binary trees Out of order field-programmable gate arrays fully pipelined vector reduction

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Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

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IEEE ACCESS 2020年 8卷 114715-114732页

作者： Saavedra, Antonio Lehnert, Hans Hernandez, Cecilia Carvajal, Gonzalo Figueroa, Miguel Tech Univ Berlin Embedded Syst Architecture Grp D-10587 Berlin Germany Univ Tecn Federico Santa Maria Dept Elect Valparaiso 2390123 Chile Univ Concepcion Dept Comp Sci Concepcion 4030000 Chile Ctr Biotechnol & Bioengn CeBiB Santiago 8370456 Chile Univ Concepcion Dept Elect Engn Concepcion 4030000 Chile

Extracting discriminative k-mers is an important and challenging problem in DNA sequence analysis with applications in metagenomics and motif discovery. Despite the availability of multiple computational tools designed for this purpose, most discriminative k-mer discovery methods suffer from long execution times and high memory usage when processing large datasets. This paper presents a novel approach for discriminative k-mer discovery in DNA sequences, which leverages streaming and sketch algorithms to reduce space complexity and expose data parallelism, enabling the use of parallel platforms for accelerating the execution of computationally-intensive operations. To assess the performance of our method, we designed and implemented two versions of the algorithm that leverage parallelization at different levels: (i) a software version tailored for multithreading and vector instructions in commodity CPUs, and (ii) a custom architecture implemented on a field-programmable gate Array (FPGA) accelerator that exploits fine-grain parallelism and deep pipelining on reconfigurable logic. Experimental results show that, when mining discriminative k-mers from a set of well-known ChIP-seq sequences, our parallel software implementation executes at least 15% faster than exact-counting tools, and requires at least five times less memory when processing large datasets. More importantly, we designed a custom FPGA-based accelerator for our algorithm on a Xilinx KCU1500 board, which achieves speedups above 78x with the largest datasets, compared to our parallel software implementation. The accelerator uses less than 3% of the logic resources available on the on-board XCKU115 Kintex-7 Ultrascale FPGA, and between 12% and 70% of the memory resources, depending on the size of the dataset.

关键词： Discriminative k-mers heavy hitters counting sketches parallel processing hardware acceleration field-programmable gate arrays

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