检索结果-内蒙古大学图书馆

Special-purpose computer for digital holographic high-speed three-dimensional imaging

OPTICAL ENGINEERING 2020年第5期59卷

作者： Yamamoto, Yota Namba, Shintaro Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Masuda, Nobuyuki Chiba Univ Grad Sch Engn Chiba Japan Tokyo Univ Sci Fac Ind Sci & Technol Tokyo Japan

Digital holography is attracting attention because it can record instantaneous three-dimensional (3D) information and record dynamic phenomena. However, when recording highspeed phenomena, the frame rate ranges from tens of thousands to hundreds of millions, and the calculation time of the reconstructed images is a problem. We have developed a special-purpose computer for high-speed 3D imaging using digital holography. The developed special-purpose computer has four calculation modules and has achieved a calculation time 68 times faster than that of a personal computer with 48 cores. With the developed computer, a total of 32 reconstructed images can be calculated in 0.69 ms from four holograms of 128 x 128 pixels with eight varying depths. (C) The Authors. Published by SPIE under a Creative Commons Attribution 4.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

关键词： optics digital holography high-speed three-dimensional imaging field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Minimalistic SDHC-SPI hardware reader module for boot loader applications

引用

MICROELECTRONICS JOURNAL 2017年 67卷 32-37页

作者： Ruiz-de-Clavijo, Paulino Ostua, Enrique Bellido, Manuel-J. Juan, Jorge Viejo, Julian Guerrero, David Univ Seville ETS Ingn Informat Dept Tecnol Elect Seville Spain

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid-and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller.

关键词： field-programmable gate array Secure Digital Boot loader Serial Peripheral Interface System on Chip Embedded systems

来源：评论

学校读者我要写书评

暂无评论

FPGA implementation of LSD-OMP for real-time ECG signal reconstruction

引用

TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2021年第4期29卷 1887-1907页

作者： Polat, Onder Kayhan, Sema Koc Gaziantep Univ Elect & Elect Engn Dept Fac Engn Gaziantep Turkey

Compressed sensing is widely used to compress electrocardiogram (ECG) signals, but the major challenges of the compressed sensing algorithms are their highly complex signal reconstruction processes. In this paper, a re-configurable high-speed and low-power field-programmable gate array (FPGA) implementation of the least support denoising-orthogonal matching pursuit (LSD-OMP) algorithm for the real-time reconstruction of the ECG signals is pre-sented. The contribution of this study is two-fold: Firstly, LSD-OMP can pick more than one element at each iteration and reconstruct the sparse signal using less number of iterations as compared to the standard OMP algorithms. Latency of the proposed design is therefore reduced by exploiting the multiple index selection feature of LSD-OMP. Secondly, the proposed architecture is the first reconfigurable LSD-OMP reconstruction architecture which can take different signal sizes and different sparsity levels. The proposed design also includes an efficient inverse wavelet transform (IWT) module to convert the reconstructed signal back into the time-domain. Together with the overhead of the IWT module, the proposed design demonstrates faster execution times while consuming lower power than the existing FPGA implemen-tations;therefore, it can be utilized in wireless body area networks as a back-end unit to reconstruct the compressed ECG signals.

关键词： field-programmable gate array electrocardiogram real-time compressed sensing

来源：评论

学校读者我要写书评

暂无评论

field programmable gate arrays implementation of automated sensor self-validation system for cupola furnaces

引用

COMPUTERS & INDUSTRIAL ENGINEERING 2004年第3期46卷 553-569页

作者： Mahmoud, WH Abdelrahman, M Haggard, RL Tennessee Technol Univ Dept Elect & Comp Engn Cookeville TN 38505 USA

The paper presents the use of an field-programmable gate array (FPGA) system in the hardware implementation of the algorithm. The self-validation (SV) algorithm is based on fuzzy logic and is used to estimate a confidence measure of a sensor's readings using the sensor's historic data. The hardware system consists of a data acquisition and conditioning system, a general-purpose CPU, and an FPGA system. The general-purpose CPU is used in the setup phase of the algorithm and in the preprocessing of the sensors' readings. The FPGA system is used in the on-line calculations of the confidence measures of the sensors' readings. The system is designed using data from an iron-melting cupola furnace. The paper presents the details of the developed SV software algorithm, the modifications of the algorithm to suit the FPGA implementation, the overall design of the hardware system, and the FPGA implementation of the algorithm. The results of the implementation are also discussed. (C) 2004 Elsevier Ltd. All rights reserved.

关键词： fuzzy controllers field-programmable gate array self-validation

来源：评论

学校读者我要写书评

暂无评论

Digitally controlled GaN-based MHz active clamp flyback converter with dynamic dead time optimisation for AC-DC adapter

引用

IET POWER ELECTRONICS 2020年第16期13卷 3777-3786页

作者： Gu, Donglie Xi, Jianxiong He, Lenian Zhejiang Univ Coll Elect Engn Hangzhou Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou Peoples R China

The active clamp flyback (ACF) converter utilising gallium nitride (GaN) devices with high-switching frequency and high efficiency is impressive in system miniaturisation for AC-DC adapters. Owing to poor reverse conduction of GaN devices, the improper dead time between two switches can cause large power consumption in high frequency. This study proposes a dynamic dead time optimisation technique for GaNs ideal zero-voltage switching (ZVS) to address the issue. It adjusts the clamp switch on time to avoid large reverse conduction voltage stress on the main switch in different loads conditions. In addition, a new control scheme for clamp switch is introduced for enhancing efficiency in light to medium load. These techniques are experimentally verified on a 45 W (20 V/2.25 A) prototype of an ACF converter with a field-programmable gate array. The controller enables the system to operate at 1 MHz and dynamically modulates the dead-time under universal input and full load. With the light load ZVS control scheme, the system can achieve a maximum efficiency of 94.12 and 80.23% in the worst case. The prototyped converter can achieve power density (exclude case and controller) of 18 W/in(3).

关键词： field programmable gate arrays switching convertors III-V semiconductors gallium compounds zero voltage switching wide band gap semiconductors digital control AC-DC power convertors circuit optimisation switches zero-voltage switching clamp switch reverse conduction voltage stress main switch load conditions ACF converter light load ZVS control scheme AC-DC adapter high-switching frequency system miniaturisation dynamic dead time optimisation technique digitally controlled gallium nitride-based MHz active clamp flyback converter gallium nitride devices power consumption field-programmable gate array power density full load universal input load power 45 0 W voltage 20 0 V current 2 25 A frequency 1 0 MHz power 18 0 W GaN

来源：评论

学校读者我要写书评

暂无评论

QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine

引用

COMPUTING IN SCIENCE & ENGINEERING 2008年第6期10卷 46-54页

作者： Goldrian, Gottfried Huth, Thomas Krill, Benjamin Lauritsen, Jack Schick, Heiko Ouda, Ibrahim Heybrock, Simon Hierl, Dieter Maurer, Thilo Meyer, Nils Schaefer, Andreas Solbrig, Stefan Streuer, Thomas Wettig, Tilo Pleiter, Dirk Sulanke, Karl-Heinz Winter, Frank Simma, Hubert Schifano, Sebastiano Fabio Tripiccione, Raffaele Nobile, Andrea Drochner, Matthias Lippert, Thomas Fodor, Zoltan IBM Res & Dev Lab Boblingen Germany IBM Lab Boblingen Germany IBM Syst & Technol Grp Rochester MN USA IBM Lab Rochester MN USA Univ Regensburg D-8400 Regensburg Germany DESY Zeuthen Germany Univ Milan I-20122 Milan Italy Univ Ferrara I-44100 Ferrara Italy European Ctr Theoret Studies Trento Italy Res Ctr Julich Inst Adv Simulat Julich Germany Julich Supercomp Ctr Julich Germany Univ Wuppertal Wuppertal Germany

Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor's multicore structure and from implementing the network processor on a field-programmable gate array.

关键词： field programmable gate arrays gauge field theory parallel machines quantum chromodynamics system-on-chip cell broadband engine field programmable gate array lattice gauge theory parallel computing system-on-chip designs QCD field-programmable gate array quantum chromodynamics chip scale packaging Network Processor String theory field programmable gate arrays parallel machines PARALLEL PROCESSING (COMPUTERS) system-on-chip Lattice gauge theory

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines

引用

IEEE ACCESS 2020年 8卷 204360-204377页

作者： Kawashima, Ichiro Morie, Takashi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka 8080196 Japan

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

关键词： Chaotic Boltzmann machines combinatorial optimization problems Ising model field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

NALLATECH IN-SOCKET FPGA FRONT-SIDE BUS ACCELERATOR

引用

COMPUTING IN SCIENCE & ENGINEERING 2010年第2期12卷 78-82页

作者： Steffen, Craig Genest, Gildas Univ Illinois US Natl Ctr Supercomp Applicat Urbana IL 61801 USA Nallatech Cumbernauld Scotland

field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.

关键词： FPGA front-side bus accelerator field-programmable gate arrays Xeon Xilinx accelerators bandwidth compiler field programmable gate arrays field-programmable gate array low-power electronics reconfigurable socket- based accelerator

来源：评论

学校读者我要写书评

暂无评论

XNORCONV: CNNs accelerator implemented on FPGA using a hybrid CNNs structure and an inter-layer pipeline method

引用

IET IMAGE PROCESSING 2020年第1期14卷 105-113页

作者： Zhang, Lin Bu, Xiaokang Li, Bing Southeast Univ Sch Integrated Circuits 2 Sipai Lou Nanjing Peoples R China

Nowadays, convolutional neural networks (CNNs) have become a research hotspot because of their high performance in computer vision and pattern recognition. However, as the high energy consumption of traditional graphic processing units-based CNNs, it is difficult to deploy them into portable devices. To deal with this problem, a hybrid CNN structure (XNORCONV) was proposed and implemented on field-programmable gate array (FPGA) in this study. Two improvements have been applied in XNORCONV. Firstly, the multiplications in the convolutional layer (CONV) were replaced by XNOR operations to save the multiplier and reduce computational complexity. Secondly, an inter-layer pipeline was designed to further accelerate the calculation. XNORCONV was implemented on Xilinx Zynq-7000 xc7z020clg400-1 under the clock frequency of 150 MHz and tested with MNIST dataset. The results of the experiment show that XNORCONV can classify each picture from MNIST in $ 18 .97\, {\rm \mu s}$18.97 mu s, and achieve 98.4% recognition accuracy. Compared with traditional Lenet-5 on different platforms, XNORCONV reduced multiplication by 85.6% with only 0.4% accuracy loss.

关键词： field programmable gate arrays logic gates convolutional neural nets neural chips multiplying circuits computational complexity pipeline processing logic design XNORCONV CNNs accelerator FPGA hybrid CNNs structure convolutional neural networks computer vision pattern recognition energy consumption graphic processing units-based CNNs field-programmable gate array convolutional layer XNOR operations multiplier computational complexity inter-layer pipeline design Xilinx Zynq-7000 xc7z020clg400-1 clock frequency MNIST dataset

来源：评论

学校读者我要写书评

暂无评论

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element

引用

IEICE TRANSACTIONS ON ELECTRONICS 2013年第4期E96C卷 473-481页

作者： Yuasa, Hiroshi Tsutsui, Hiroshi Ochi, Hiroyuki Sato, Takashi Kyoto Univ Grad Sch Informat Dept Commun & Comp Engn Kyoto 6068501 Japan

We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116 MHz clock rate. A speedup of far more than x10 is achieved compared to conventional methods including GPU implementation.

关键词： statistical static timing analysis delay distribution slew rate field-programmable gate array Mersenne Twister

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：