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Performance evaluation of FPGA-based predictive current controller for FL-DSTATCOM in electric distribution system

IET GENERATION TRANSMISSION & DISTRIBUTION 2019年第19期13卷 4400-4409页

作者： Dheepanchakkravarthy, Azhagesan Jawahar, Marappan Rakkiannan Venkatraman, Kandadai Selvan, Manickavasagam Parvathy Moorthi, Sridharan Bannari Amman Inst Technol Dept Elect & Elect Engn Sathyamangalam India Natl Inst Technol Dept Elect & Elect Engn Hybrid Elect Syst Lab Tiruchirappalli 620015 Tamil Nadu India Vardhaman Coll Engn Dept Elect & Elect Engn Hyderabad India

A four-leg distribution static compensator (FL-DSTATCOM) has been employed for improving the quality of power in electric distribution system using field-programmable gate array (FPGA). A predictive current control technique without any modulation scheme is utilised to generate switching pulses for FL-DSTATCOM using a cost function defining the preferred system behaviour. This technique makes the supply current as balanced and sinusoidal by exactly tracking the reference current, compensating the reactive power, maintaining near unity power factor and nullifies the current flow in neutral conductor during steady and dynamic state conditions. Synchronous reference frame theory is effectively implemented for extracting the reactive and harmonic part of load current which are the primary components in the evaluation of reference currents. The predictive current control scheme implemented in FPGA has been deployed to evaluate the behaviour of the FL-DSTATCOM under multifarious loading conditions.

关键词： field programmable gate arrays predictive control power factor electric current control static VAr compensators power distribution control digital control power supply quality reactive power FL-DSTATCOM electric distribution system four-leg distribution static compensator field-programmable gate array supply current unity power factor current flow load current performance evaluation FPGA-based predictive current controller system behaviour reactive power compensation power quality switching pulse generation cost function reference current tracking neutral conductor dynamic state conditions steady state conditions synchronous reference frame theory reference current evaluation multifarious loading conditions near unity power factor

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A resource saving FPGA implementation approach to fractional Kalman filter

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IET CONTROL THEORY AND APPLICATIONS 2022年第13期16卷 1352-1363页

作者： Xu, Bo Bai, Libing Chen, Kai Tian, Lulu Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Peoples R China

The efficiency of the hardware implementations of fractional Kalman filter (FKF) heavily relies on the efficiency of realising the fractional-order derivative operator. In this paper, a generic software and hardware implementation of the FKF based on the Grunwald-Letnikov approximation is proposed and verified on a field-programmable gate array. The main advantage of this particular realisation is its resource saving capability on both software and hardware components (e.g. digital signal processing chips), and this enables fast and efficient real-time computation of the FKF. Furthermore, the performance of the FKF is evaluated via studying the mean square boundedness of the filtering error. At last, a mass-spring-damper example is implemented via Matlab simulations to verify the applicability of the proposed approach and moreover, a hardware experiment is also conducted to demonstrate the advantage of resource saving.

关键词： digital signal processing chips software components hardware experiment filtering error Grunwald-Letnikov approximation field-programmable gate array FKF generic software hardware implementation fractional-order derivative operator field programmable gate arrays fractional Kalman filter approximation theory particular realisation hardware-software codesign FPGA implementation approach mean square boundedness hardware components hardware implementations mass-spring-damper Matlab simulations Kalman filters

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Ion current-based homogeneous charge compression ignition combustion control using direct water injection

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INTERNATIONAL JOURNAL OF ENGINE RESEARCH 2021年第6期22卷 1825-1837页

作者： Zhu, Denghao Deng, Jun Dewor, Raphael Wick, Maximilian Andert, Jakob Li, Liguang Tongji Univ Shanghai 201804 Peoples R China Rhein Westfal TH Aachen Inst Tech Thermodynam Aachen Germany FEV Europe GmbH Aachen Germany Rhein Westfal TH Aachen Mechatron Syst Combust Engines Aachen Germany

Homogeneous charge compression ignition has proven to be both highly efficient and to operate with ultra-low NOx raw emissions. However, homogeneous charge compression ignition combustion is a dynamic process due to strong cycle-to-cycle coupling effects caused mainly by the residual gas. Compared to conventional spark-ignited and diesel engines, the lack of direct mixture composition and ignition control increases the challenge of combustion instabilities, especially at boundary conditions. To stabilize the combustion process, real-time in-cylinder combustion diagnostics and control are often used. In this study, for the first time, ion current detection technology and direct water injection are combined for homogeneous charge compression ignition combustion control. By analyzing the return map of the crank angle at 50% cumulative heat release under unstable conditions, it was identified that a misfire or incomplete combustion is usually followed by knocking-like early combustion with high cylinder pressure gradients. Through the correlation analysis between ion current and combustion, a cycle-to-cycle closed-loop control strategy was developed and implemented on a rapid control prototyping engine control unit. Real-time calculated ion current parameters were used to predict the 50% cumulative heat release position of the next cycle and prevent early combustion by direct water injection. The calculation results and controller performance were validated on a single-cylinder research engine. With the controller activated, the standard deviation of 50% cumulative heat release and dynamic programming to the max could be reduced by 19% and 11%, respectively. The coefficient of variation of indicated mean effective pressure was reduced by 12%. A slight increase in indicated mean effective pressure after activating the controller also shows the potential for efficiency improvement. Moreover, not only early combustion is controlled, but also late combustion is significantl

关键词： Ion current homogeneous charge compression ignition gasoline controlled autoignition field-programmable gate array combustion control water injection

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Implementation of modulation classifier over software defined radio

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IET COMMUNICATIONS 2020年第9期14卷 1467-1475页

作者： Jajoo, Gaurav Kumar, Yogesh Kumar, Ashok Yadav, Sandeep Kumar Dept Elect Engn NH 65 Jodhpur Rajasthan India DRDO Sci Anal Grp Sag Delhi India

Blind signal modulation recognition is an essential block for designing a cognitive radio. Different algorithms are developed in the literature, but few are given with detailed implementation. This study proposes a software-defined radio based implementation of blind signal modulation recogniser (BSMR) on field-programmable gate array (FPGA), which works without any prior knowledge of the received signal. The algorithm estimates carrier frequency offset, symbol rate, symbol timing offset, and corrects the signal for these offsets to extract constellation points. It uses clustering structure formed by constellation signature in I/Q plane to detect the modulation for different orders of ASK, PSK, and QAM. The proposed algorithm is deployed on FPGA, using LabVIEW, for a reliable and reconfigurable platform. The algorithm is optimised to use minimum hardware resources and facilitate future up-gradation. The system developed by implementing the algorithm on NI-FlexRIO-7975 FPGA module with NI-5791 adapter detects modulation type in real time without any training. Signals for testing are generated using NI-PXIe-5673 (RF transmitter), and BSMR identifies the modulation type in 81.451ms under additive white Gaussian noise channel.

关键词： virtual instrumentation phase shift keying cognitive radio field programmable gate arrays quadrature amplitude modulation AWGN channels software radio amplitude shift keying pattern classification pattern clustering BSMR modulation classifier blind signal modulation recognition cognitive radio software-defined radio blind signal modulation recogniser field-programmable gate array received signal carrier frequency offset symbol rate symbol timing offset constellation points constellation signature NI-FlexRIO-7975 FPGA module NI-5791 adapter clustering structure ASK PSK QAM LabVIEW reconfigurable platform RF transmitter additive white Gaussian noise channel

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A compact hardware architecture for digital image stabilization using integral projections

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MICROPROCESSORS AND MICROSYSTEMS 2015年第8期39卷 987-997页

作者： Araneda, Luis Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Ctr Opt & Photon CEFOP Concepcion Chile

We present a hardware architecture for real-time digital video stabilization for high-performance embedded systems. The stabilization algorithm analyzes the current and past video frames and obtains a motion estimation vector, which is then filtered to isolate unwanted camera movements from intentional panning. The vector is then used to correct the output video frame. The paper describes our hardware architecture for motion estimation, filtering and correction and its implementation on a Xilinx Spartan-6 LX45 FPGA. We evaluate our results on several benchmark video sequences, both visually and using the Inter-frame Transformation Fidelity index (ITF). Running on the 640 x 480-pixel video output of an infrared camera, our FPGA implementation successfully compensates involuntary camera motion at a maximum throughput of 104.15 frames per second with a 100 MHz clock. The power consumption added to the FPGA by the image stabilization core is only 24.16 mW. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Embedded video processing field-programmable gate array Digital image stabilization Integral projections

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Dual-model predictive control of two independent induction motors driven by a SiC nine-switch inverter

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INTERNATIONAL JOURNAL OF ELECTRONICS 2023年第1期110卷 124-142页

作者： Gokdag, Mustafa Gulbudak, Ozan Karabuk Univ Dept Elect Elect Engn Karabuk Turkey

This paper presents a finite control set model predictive control (FCS-MPC) approach for two induction machines driven by a nine-switch inverter (NSI). In the traditional approach, two separate voltage source inverters are necessary to drive the independent induction motors. In the proposed method, the nine-switch inverter is used to control the separate motors with a reduced number of switching devices compared to traditional method. A robust control strategy that eliminates the interactions between separate mechanical loads is required to achieve a proper independent speed and torque control for two induction machines through the NSI. To ensure the reliability of the machine operation, the indirect-field oriented control-based model predictive control strategy is proposed. The proposed control strategy is experimentally validated across the 3.2 kW SiC-based NSI prototype. The control algorithm is performed on an Altera Cyclone IV field-programmable gate array. The experimental results demonstrate that the proposed dual-model predictive control method provides a good and robust motor control operation under different loading conditions. Two induction motors are successfully controlled, and the independent speed and torque control are achieved.

关键词： Nine-switch inverter multi-drive systems multi-machines model predictive control indirect field-oriented control field-programmable gate array

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Accurate multiple-input multiple-output fading channel simulator using a compact and high-throughput reconfigurable architecture

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IET COMMUNICATIONS 2011年第6期5卷 844-852页

作者： Alimohammad, A. Fard, S. F. Cockburn, B. F. Ukalta Engn Edmonton AB T5J 4P6 Canada Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

This article presents an ultra-compact and high-throughput reconfigurable fading channel simulator that supports a relatively large number of propagation paths. To closely reflect actual radio channels, the authors used a recently improved Rayleigh and Ricean fading channel model based on the sum-of-sinusoids technique. The improved model is optimised for hardware compactness. To achieve a fast fading variate generation rate with much less hardware and no significant loss in accuracy, the new scheme first generates fading samples at a lower rate using a time-multiplexed datapath that can be fit into a small fraction of a field-programmable gate array (FPGA). In the second step, the simulator uses a compact multiplication-free linear interpolator to produce the fading samples at the full symbol rate. Implementing a 64-path fading channel simulator on a Xilinx Virtex-4 XC4VLX200-11 FPGA requires only 13 044 (14%) of the configurable slices, 10 (2%) of the block memories and one (1%) of the dedicated DSP blocks, while generating 64 x 191 million complex-valued fading samples per second. The simulated paths can be readily combined to form high path count models for multiple-input multiple-output systems as well as frequency-selective channels.

关键词： ultracompact reconfigurable architecture DSP blocks propagation paths fast fading variate generation rate 64-path fading channel simulator time-multiplexed datapath compact multiplication-free linear interpolator frequency-selective channels radio signal propagation conditions Logic circuits interpolation high-throughput reconfigurable architecture radiowave propagation Rayleigh fading channel model Radiowave propagation sum-of-sinusoids technique field programmable gate arrays field-programmable gate array Rician channels Xilinx Virtex-4 XC4VLX200-11 FPGA Ricean fading channel model Interpolation and function approximation (numerical analysis) Radio links and equipment multiple-input multiple-output fading channel simulator Rayleigh channels MIMO communication

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Hardware-Efficient Design and Implementation of a Spiking Neural Model With Noisy Astrocyte

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IEEE ACCESS 2023年 11卷 100180-100194页

作者： Gholami, Morteza Karimi, Gholamreza Linares-Barranco, Bernabe Razi Univ Fac Elect & Comp Engn Elect Engn Dept Kermanshah *** Iran CSIC Inst Microelect Sevilla IMSE CNM Seville 41092 Spain Univ Seville Seville 41092 Spain

Neuromorphic architectures are systems that aim at using the principles of biological neural functions as their basis of operation. One of the most significant challenges in neuromorphic studies, which play an important role in information processing, is the investigation of astrocytes in neuronal models. This paper presents an efficient FPGA-based digital implementation of a spiking neuron model, known as the 2D Hindmarsh-Rose model, and neuron-astrocyte model. To avoid costly computations, the astrocyte and 2D Hindmarsh-Rose models were approximated. The approximation was performed based on multiple method such as the piecewise linear model (PWL) and the particle swarm optimization (PSO) method. As known, noisy mechanisms are stochastic processes which help to improve information processing in nonlinear dynamical systems, including neural systems, and results in more realistic behaviors. Therefore, we presented the noise implications for the approximated neuron-astrocyte models. By introducing two networks consisting of ten 2D Hindmarsh-Rose neurons, the role of the approximated astrocyte in regulation of the neural activities and noise tolerance of the neural networks was investigated. Accordingly, the feasibility of the digital implementation for the proposed 2D Hindmarsh-Rose neuron and the neuron-astrocyte models was studied. Experimental findings of the hardware synthesis and physical implementation on a field-programmable gate array (FPGA) were expounded for the modified spiking neuron model and the approximated astrocyte models with maximum clock frequencies of 247.35 MHz and 279.28 MHz, respectively, showed an increase by about 3.5 times in the frequency in both approximated models. The number of slice registers decreased by 22% and 20% in the proposed 2D Hindmarsh-Rose and astrocyte models, respectively. Also, the networks in the original and approximated 2D Hindmarsh-Rose neurons and astrocyte were synthesized on an FPGA platform. Maximum clock frequenci

关键词： field-programmable gate array Hindmarsh-Rose neuron model neuromorphic architectures spiking neuron model noisy astrocyte multiplierless implementation

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Lower complexity error location detection block of adjacent error correcting decoder for SRAMs

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IET COMPUTERS AND DIGITAL TECHNIQUES 2020年第5期14卷 210-216页

作者： Maity, Raj Kumar Tripathi, Sayan Samanta, Jagannath Bhaumik, Jaydeb Haldia Inst Technol Dept ECE Haldia W Bengal India Jadavpur Univ Dept ETCE Kolkata India

Multiple cell upsets (MCUs) caused by radiation is an important issue related to the reliability of embedded static random access memories (SRAMs). Multiple random and adjacent error correcting codes have been extensively employed for several years to protect stored data in SRAMs against MCUs. A compact and fast error correcting codec is desirable in most of these applications. In this study, simplified expressions for error location detection (ELD) block for single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) and single error correction-double error detection-triple adjacent error correction (SEC-DED-TAEC) decoders have been obtained by employing Karnaugh map. The conventional SEC-DED-DAEC and SEC-DED-TAEC decoders have been designed and implemented in both field-programmable gate array and ASIC platforms by considering these simplified ELD expressions. In FPGA platform, the proposed design for SEC-DED-DAEC and SEC-DED-TAEC decoders require 1.37-28.40% improvement in area and maximum 14.74% improvement in delay compared to existing designs. Whereas ASIC-based designs provide 2.20-26.81% reduction in area and 0.30-28.96% reduction in delay compared to existing related works. So the proposed design can be considered as an efficient alternative of traditional adjacent error correcting decoders in resource constraint applications.

关键词： field programmable gate arrays SRAM chips decoding error detection codes application specific integrated circuits error correction codes adjacent error correcting decoder SRAM multiple random error correcting codes adjacent error correcting codes conventional SEC-DED-DAEC SEC-DED-TAEC decoders error location detection block error correction-double error detection error correcting codec multiple cell upsets static random access memories -triple adjacent error correction Karnaugh map field-programmable gate array ASIC platforms resource constraint applications

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Area-efficient and scalable solution to real-data fast fourier transform via regularised fast Hartley transform

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IET SIGNAL PROCESSING 2007年第3期1卷 128-138页

作者： Jones, K. J. Coster, R. L 3 Commun TRL Technol Tewkesbury GL20 8ND Glos England

A highly parallel hardware solution to the regularised fast Hartley transform (FHT), an algorithm developed only recently for the efficient computation of the discrete Hartley transform (DHT) and hence of the real-data fast Fourier transform (FFT), is discussed. A drawback of conventional FHT algorithms lies in the loss of regularity arising from the need for two types of, butterfly' for catering for fixed-radix formulations. A generic radix-4 double butterfly was therefore developed for the regularised FHT which overcame the problem in an elegant fashion. An architecture for the parallel computation of the generic double butterfly and the resulting regularised FHT is now discussed in some detail;this exploits a single high-performance processing element (PE) which yields an attractive solution, particularly when implemented with field-programmable gate array (FPGA) technology, which is both area-efficient and scalable in terms of transform length. High performance is achieved by having the PE able to process the input/ output data sets to the double butterfly in parallel, this in turn implying the need to be able to access simultaneously, and without conflict, both multiple data and multiple twiddle factors, or coefficients, from their respective memories. The resulting area-efficient and scalable single-PE architecture is shown to yield a generic solution to the real-data FFT which is capable of achieving the throughput of the most advanced commercially available solutions for just a fraction of the silicon area and, for new applications, at negligible re-design cost.

关键词： real-data fast Fourier transform area-efficient solution scalable solution digital signal processing regularised fast Hartley transform generic double butterfly radix-4 double butterfly discrete Hartley transforms field-programmable gate array Integral transforms in numerical analysis fast Fourier transforms high-performance processing element discrete Hartley transform highly parallel hardware solution fast Fourier transform fixed-radix formulation Integral transforms signal processing multiple twiddle factors

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