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Resource-constrained FPGA/DNN co-design

NEURAL COMPUTING & APPLICATIONS 2021年第21期33卷 14741-14751页

作者： Zhang, Zhichao Kouzani, Abbas Z. Deakin Univ Sch Engn Geelong Vic 3216 Australia

Deep neural networks (DNNs) have demonstrated super performance in most learning tasks. However, a DNN typically contains a large number of parameters and operations, requiring a high-end processing platform for high-speed execution. To address this challenge, hardware-and-software co-design strategies, which involve joint DNN optimization and hardware implementation, can be applied. These strategies reduce the parameters and operations of the DNN, and fit it into a low-resource processing platform. In this paper, a DNN model is used for the analysis of the data captured using an electrochemical method to determine the concentration of a neurotransmitter and the recoding electrode. Next, a DNN miniaturization algorithm is introduced, involving combined pruning and compression, to reduce the DNN resource utilization. Here, the DNN is transformed to have sparse parameters by pruning a percentage of its weights. The Lempel-Ziv-Welch algorithm is then applied to compress the sparse DNN. Next, a DNN overlay is developed, combining the decompression of the DNN parameters and DNN inference, to allow the execution of the DNN on a FPGA on the PYNQ-Z2 board. This approach helps avoid the need for inclusion of a complex quantization algorithm. It compresses the DNN by a factor of 6.18, leading to about 50% reduction in the resource utilization on the FPGA.

关键词： Lempel-Ziv-Welch compression Deep neural network Hardware-and-software co-design Electrochemical sensing field-programmable gate array

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Analysis and FPGA Implementation of Zero-Forcing Receive Beamforming with Signal Space Diversity under Different Interleaving Techniques

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2020年第1期29卷

作者： Resat, Mustafa Anil Cicek, Adem Ozyurt, Serdar Cavus, Enver Ankara Yildirim Beyazit Univ Dept Elect & Elect Engn Ankara Turkey

We combine multiple-input multiple-output zero-forcing receive beamforming (ZFRBF) with time and spatial component interleaved signal space diversity (SSD) and analyze the system's error performance and implementation complexity. A transreceiver system with two transmit and M >= 2) receive antennas is considered where the number of simultaneous substreams equals two. The error performance of the proposed scheme with binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) modulations is studied. Under the time component interleaved SSD case, we derive an exact average bit error probability expression for BPSK and a tight approximation on the average symbol error probability for QPSK. The signal constellation rotation angles are accordingly computed. Using a similar approach, the signal constellation rotation angles are also determined for the scenario of spatial component interleaved SSD. It is demonstrated that the performance of the original ZFRBF model can be improved significantly by utilizing SSD especially with the time interleaving method. Another contribution to the literature is to study hardware complexity of the proposed scheme on FPGA. It is shown that while achieving considerable performance gain, SSD introduces only an insignificant increase to the system complexity without any extra bandwidth or time slot usage.

关键词： Signal space diversity multiple-input multiple-output zero-forcing receive beamforming time interleaving spatial interleaving field-programmable gate array

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Real-Time FPGA Investigation of Interplay Between Probabilistic Shaping and Forward Error Correction

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2022年第5期40卷 1339-1345页

作者： Zhang, Liangjun Tao, Kai Qian, Weifeng Wang, Weiming Liang, Junpeng Cai, Yi Feng, Zhenhua ZTE Corp State Key Lab Mobile Network & Mobile Multimedia Wuhan 430233 Peoples R China ZTE TX Inc Morristown NJ 07960 USA Soochow Univ Suzhou Jiangsu Peoples R China

In this work, we implement a complete probabilistic amplitude shaping (PAS) architecture on a field-programmable gate array (FPGA) platform to study the interplay between probabilistic shaping (PS) and forward error correction (FEC). Due to the fully parallelized input-output interfaces based on look up table (LUT) and low computational complexity without high-precision multiplication, hierarchical distribution matching (HiDM) is chosen as the solution for real time probabilistic shaping. In terms of FEC, we select two kinds of the mainstream soft decision-forward error correction (SD-FEC) algorithms currently used in optical communication system, namely Open FEC (OFEC) and soft-decision quasi-cyclic low-density parity-check (SD-QC-LDPC) codes. Through FPGA experimental investigation, we studied the impact of probabilistic shaping on OFEC and LDPC, respectively, based on PS-16QAM under moderate shaping, and also the impact of probabilistic shaping on LDPC code based on PS-64QAM under weak/strong shaping. The FPGA experimental results show that if pre-FEC bit error rate (BER) is used as the predictor, moderate shaping induces no degradation on the OFEC performance, while strong shaping slightly degrades the error correction performance of LDPC. Nevertheless, there is no error floor when the output BER is around 10(-15). However, if normalized generalized mutual information (NGMI) is selected as the predictor, the performance degradation of LDPC will become insignificant, which means pre-FEC BER may not a good predictor for LDPC in probabilistic shaping scenario. We also studied the impact of residual errors after FEC decoding on HiDM. The FPGA experimental results show that the increased BER after HiDM decoding is within 10 times compared to post-FEC BER.

关键词： field programmable gate arrays Parity check codes Forward error correction Real-time systems Probabilistic logic Table lookup Random access memory Distribution matching field-programmable gate array forward error correction optical fiber communication probabilistic shaping

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Model Predictive Control Strategy for Induction Motor Drive Using Lyapunov Stability Objective

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2022年第12期69卷 12119-12128页

作者： Gulbudak, Ozan Gokdag, Mustafa Komurcugil, Hasan Karabuk Univ Dept Elect Elect Engn TR-78050 Karabuk Turkey Eastern Mediterranean Univ Dept Comp Engn TR-99628 Famagusta Turkey

This article presents a novel Lyapunov-based model predictive control strategy for squirrel-cage induction motor fed by a voltage source inverter. The model predictive control method has received enormous attention thanks to its rapid response to load perturbations. However, the traditional model predictive control method may suffer from instability due to the poor choice of the objective function, weighting factors, or other design parameters. In particular, the selection of the objective function may not be sufficient to ensure global stability. Since the performance of the model predictive control method highly relies on the explicit model of the system, a simple penalization term in the objective function can lead to system instability. As a result, the transient and steady-state performances are negatively affected. The objective function is reformulated as the Lyapunov energy function to deal with this ambiguous situation in this article. The control input constraints are defined in the formulated optimal control problem, and the optimal solution is explored by assessing the Lyapunov stability criterion. The proposed method ensures asymptotic stability since the control action that satisfies the Lyapunov stability condition is selected. The experimental work proves the theoretical concepts. Moreover, the proposed method does not require the weighting factors to control the multiple control goals. The experimental results demonstrate that the proposed control strategy improves the steady-state performance. The machine torque and speed are well regulated, and the quality of the stator current is improved.

关键词： field-programmable gate array induction motor Lyapunov method model predictive control voltage-source inverter

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Real-Time Digital Compensation of Current Transformers Over a Wide Frequency Range

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2010年第5期59卷 1119-1126页

作者： Gallo, Daniele Landi, Carmine Luiso, Mario Univ Naples 2 Dept Informat Engn I-81031 Aversa Italy

The advance in power electronics causes, over the years, an increasing diffusion of nonlinear loads. Moreover, electrical generation systems are going to include a growing amount of solar and wind energy, characterized by time-variant flow of energy and, very often, with a relevant distortion. These aspects give more and more emphasis to the monitoring of conducted disturbances on power systems over a wide frequency range, and consequently, voltage and current transducers adopted for this aim must have a proper frequency bandwidth. Voltage transformers (VTs) and current transformers (CTs), which are the most installed transducers in electrical power systems, are typically constructed to operate only at the industrial frequency, i.e., 50/60 Hz, but it is clear that their substitution would require an unsustainable cost. Therefore, in this paper, a method for real-time digital compensation of the CT frequency response over a wide range is presented. An implementation of the proposed method is shown, and the compensated CT is characterized and tested in some practical situations, with waveforms affected by typical power quality disturbances.

关键词： Compensation current transformer (CT) digital filter field-programmable gate array frequency response power quality

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FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2021年第5期26卷 1–39页

作者： Feng, Lang Huang, Jeff Hu, Jiang Reddy, Abhijith Nanjing Univ 163 Xianlin Rd Nanjing 210023 Peoples R China Texas A&M Univ 400 Bizzell St College Stn TX 77840 USA

Control-Flow Integrity (CFI) is an effective defense technique against a variety of memory-based cyber attacks. CFI is usually enforced through software methods, which entail considerable performance overhead. Hardware-based CFI techniques can largely avoid performance overhead, but typically rely on code instrumentation, forming a non-trivial hurdle to the application of CFI. Taking advantage of the tradeoff between computing efficiency and flexibility of FPGA, we develop FastCFI, an FPGA-based CFI system that can perform fine-grained and stateful checking without code instrumentation. We also propose an automated Verilog generation technique that facilitates fast deployment of FastCFI, and a compression algorithm for reducing the hardware expense. Experiments on popular benchmarks confirm that FastCFI can detect fine-grained CFI violations over unmodified binaries. When using FastCFI on prevalent benchmarks, we demonstrate its capability to detect fine-grained CFI violations in unmodified binaries, while incurring an average of 0.36% overhead and a maximum of 2.93% overhead.

关键词： Control-flow integrity field-programmable gate array security

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FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures

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INTEGRATION-THE VLSI JOURNAL 2021年 81卷 175-194页

作者： Anandakumar, N. Nalla Hashmi, Mohammad S. Tehranipoor, Mark Univ Florida Elect & Comp Engn Dept Gainesville FL 32611 USA Nazarbayev Univ Sch Engn & Digital Sci Astana 010000 Kazakhstan

Physically Unclonable Functions (PUFs) are a promising technology and have been proposed as central building blocks in many cryptographic protocols and security architectures. Among other uses, PUFs enable chip identifier/authentication, secret key generation/storage, seed for a random number generator and Intellectual Property (IP) protection. field programmable gate arrays (FPGAs) are re-configurable hardware systems which have emerged as an interesting trade-off between the versatility of standard microprocessors and the efficiency of Application Specific Integrated Circuits (ASICs). In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. PUF technology can protect the individual FPGA IP cores with less overhead. In this article, we first provide an extensive survey on the current state-of-the-art of FPGA based PUFs. Then, we provide a detailed performance evaluation result for several FPGA based PUF designs and their comparisons. Subsequently, we briefly report on some of the known attacks on FPGA based PUFs and the corresponding countermeasures. Finally, we conclude with a brief overview of the FPGA based PUF application scenarios and future research directions.

关键词： Physical Unclonable Functions (PUFs) field-programmable gate array Hardware security PUF applications FPGA based PUFs

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THx2 programmable Logic Block Architecture for Clockless Asynchronous FPGAs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第7期69卷 2906-2915页

作者： Emmert, John M. Perumalla, Anvesh K. Hudson, Tristan J. Concha, Luis M. Univ Cincinnati Dept Elect Engn & Comp Sci Cincinnati OH 45221 USA

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our THx2 programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The THx2 threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the THx2 threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the THx2 threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the THx2 threshold cell-along with the symmetry of the mask- and field-programmable gate array logic cells-made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

关键词： Computer architecture Logic gates Microprocessors field programmable gate arrays Trojan horses Layout Wires Assurance asynchronous field-programmable gate array mask-programmable gate array null convention logic programmable logic block security side-channel attacks split manufacturing threshold gates trust

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IBM POWER9 PROCESSOR ARCHITECTURE

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IEEE MICRO 2017年第2期37卷 40-51页

作者： Sadasivam, Satish Kumar Thompto, Brian W. Kalla, Ron Starke, William J. IBM Corp Armonk NY 10504 USA IBM Corp Power Syst Processor Team Armonk NY 10504 USA IBM Corp Power9 Armonk NY 10504 USA

THE IBM POWER9 PROCESSOR HAS AN ENHANCED CORE AND CHIP ARCHITECTURE OPTIMIZED FOR EMERGING WORKLOADS WITH SUPERIOR THREAD PERFORMANCE AND HIGHER THROUGHPUT TO SUPPORT NEXT-GENERATION COMPUTING. MULTIPLE VARIANTS OF SILICON TARGET THE SCALE-OUT AND SCALE-UP MARKETS. WITH A NEW CORE MICROARCHITECTURE DESIGN, ALONG WITH AN INNOVATIVE I/O FABRIC TO SUPPORT ACCELERATED COMPUTING REQUIREMENTS, THE POWER9 PROCESSOR MEETS THE DIVERSE COMPUTING NEEDS OF THE COGNITIVE ERA AND PROVIDES A PLATFORM FOR ACCELERATED COMPUTING.

关键词： accelerator cache CAPI Computer architecture field programmable gate arrays field-programmable gate array FPGA GPU Graphics processing units I/O Instruction sets interconnects memory microarchitecture multicore Multicore processing Multiprocessing systems POWER9 processor simultaneous multithreading SMP SMT Switched mode power supplies symmetric multiprocessor

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Performance-driven placement for dynamically reconfigurable FPGAs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2002年第4期7卷 628-642页

作者： Wu, GM Lin, JM Chang, YW Han Hua Univ Dept Informat Management Dalin Chiayi 22 Taiwan Realtek Semicond Corp Hsinchu Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10764 Taiwan

In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2, 27.0, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.

关键词： algorithms design experimentation measurement performance computer-aided design of VLSI dynamically reconfigurable layout placement field-programmable gate array

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