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High-resolution detection of sustained ventricular and supraventricular tachycardia through FPGA-based fuzzy processing of ECG signal

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MEDICAL & BIOLOGICAL ENGINEERING & COMPUTING 2015年第10期53卷 1037-1047页

作者： Chowdhury, Shubhajit Roy Indian Insitute Technol Mandi Sch Comp & Elect Engn Mandi 175005 Himachal Prades India

The paper presents a field-programmable gate array (FPGA)-based fast processing system with 12-channel high-resolution (24 bits) front-end for ECG signal processing. The implemented high-resolution data conversion makes the system suitable for recording of late potentials of the QRS complex in patients prone to sustained ventricular tachycardia. The system accepts ECG signals through 12 channels and then filtered to minimize baseline wander and power-line interference. The filter outputs are connected to 12 delta-sigma ADCs. The whole ADCs work synchronously at 8 kHz sampling frequency, and their output data are transferred to an FPGA that computes online on the digitized sample values in real time and ascertains whether the patient under study suffers from ventricular tachycardia or not. In order to ascertain the QRS complex accurately in the noisy ECG signal, fuzzy entropy of the sample values has been computed and provided as an input to inverse multiquadratic radial basis function neural network. Using the standard CSE ECG database, the algorithm performed highly effectively. The performance of the algorithm in respect of QRS detection with sensitivity of 99.83 % and accuracy of 99.7 % is achieved when tested using single-channel ECG with entropy criteria. The performance of the QRS detection system has been compared and found to be better than most of the QRS detection systems available in the literature. Using the system, 200 patients have been diagnosed with an accuracy of 99 %.

关键词： field-programmable gate array ECG Ventricular tachycardia Differential diagnosis

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Design and Implementation of an FPGA-based Real-time Simulator for a Dual Three-Phase Induction Motor Drive

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JOURNAL OF POWER ELECTRONICS 2016年第2期16卷 553-563页

作者： Gregor, Raul Valenzano, Guido Rodas, Jorge Rodriguez-Pineiro, Jose Gregor, Derlis Univ Nacl Asuncion Fac Ingn Lab Power & Control Syst Asuncion Paraguay Univ A Coruna Dept Elect & Syst Coruna Spain Univ Nacl Asuncion Fac Ingn Lab Distributed Syst Asuncion Paraguay

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

关键词： Device simulation field-programmable gate array Multiphase drive Real-time simulation

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Step-up Transformerless Seven-level DC-AC Hybrid Topology for Interconnection of Renewable-based DC Sources to Microgrids

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ELECTRIC POWER COMPONENTS AND SYSTEMS 2014年第16期42卷 1792-1801页

作者： Ramon Rodriguez, Juan Lenimirko Moreno-Goytia, Edgar Venegas Rebollar, Vicente Eduardo Ugalde, Luis Maria Salgado-Herrera, Nadia Inst Tecnol Morelia Morelia 58120 Michoacan Mexico Inst Tecnol Morelia Dept Elect & Elect Engn Morelia 58120 Michoacan Mexico Inst Tecnol Morelia Postgrad Studies Program Elect Engn Morelia 58120 Michoacan Mexico Univ Michoacana Morelia Michoacan Mexico

This article introduces a new step-up transformerless multi-level DC-AC hybrid topology for interconnecting renewable DC sources to loads or microgrids. This enabling technology incorporates the best characteristics of three modified basic topologies-a DC-DC multi-level boost converter, a DC-DC multi-level buck converter, and an H-bridge-to obtain a seven-level step-up DC-AC hybrid structure using only one DC input and nine power switches for a single-phase output with field-programmable gate array based control. The advantages of the step-up seven-level structure compared to other proposals are higher efficiency, a reduced number of power switches, and high power density associated with transformerless characteristic. Furthermore, in contrast to conventional topologies, the proposed design does not require voltage/current monitoring of the capacitors or a capacitor-balancing control scheme, and only one DC source input is used. Consequently, a high-performance configuration is obtained. The laboratory results demonstrate the validity of the design and the performance of the prototype.

关键词： transformerless microgrids multi-level boost converter DC-DC converter DC-AC converter field-programmable gate array multi-level buck converter

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Design for High-Precision Time-Sensitive Networking: Synchronization for the Quantum Network Control Plane

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 2024年第7期42卷 1861-1870页

作者： Bush, Stephen F. Iversen, Christopher G. Challener, William A. Gen Elect Res Niskayuna NY 12309 USA ForwardEdge ASIC St Paul MN 55108 USA Gen Elect Res Ctr Niskayuna NY 12309 USA

Tight integration between classical and quantum networking requires strict synchronization of events between the classical and quantum portions of the network. Time-Sensitive Networking (TSN) as defined by IEEE 802.1Q is limited to accuracy on the order of microseconds due to limitations in time synchronization performance;TSN gate control is thus similarly limited. This work presents a new High-Precision TSN that enables greater accuracy and resolution toward sub-nanosecond TSN gate control and can directly support entanglement distribution, a key component in a software-designed quantum network architecture where classical control can reach deep into the quantum network and directly control time critical operations.

关键词： Photonics Quantum networks Detectors Synchronization Quantum entanglement Logic gates Real-time systems Control plane field-programmable gate array network management quantum channels quantum communication quantum networks quantum network architecture quantum optics real-time control real-time systems software-defined network timing synchronization time-sensitive network

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In-Memory Data Rearrangement for Irregular, Data-Intensive Computing

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COMPUTER 2015年第8期48卷 18-25页

作者： Lloyd, Scott Gokhale, Maya Lawrence Livermore Natl Lab Livermore CA 94550 USA

The data rearrangement engine (DRE) performs in-memory data restructuring to accelerate irregular, data-intensive applications. An emulation on a field-programmable gate array shows how the DRE could improve speedup, ... 详细信息

关键词： field programmable gate arrays DRE data rearrangement engine energy consumption improvement field-programmable gate array in-memory data rearrangement in-memory data restructuring irregular-data-intensive application acceleration memory bandwidth improvement speedup improvement Computer applications Emulation field programmable gate arrays Memory management Stacked memory 3D stacked memory FPGA emulation active memory data rearrangement engine data-intensive computing irregular applications processing in memory

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High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2023年第4期16卷 1-23页

作者： Yingchun Lu Yun Yang Rong Hu Huaguo Liang Maoxiang Yi Huang Zhengfeng Yuanming Ma Tian Chen Liang Yao Hefei Univ Technol Sch Microelect 193 Tunxi Rd Hefei 230601 Anhui Peoples R China Hefei Univ Technol Sch Comp & Informat Technol 193 Tunxi Rd Hefei 230601 Anhui Peoples R China Anhui Univ Sch Integrated Circuits 111 Jiulong Rd Hefei 230039 Anhui Peoples R China

Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, and so on. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550 Mbps and 1,100 Mbps, respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.

关键词： True random number generator field-programmable gate array Dual-ring oscillator

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Multi-core DSP-based Vector Set Bits Counters/Comparators

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2015年第3期80卷 309-322页

作者： Sklyarov, Valery Skliarova, Iouliia Univ Aveiro Dept Elect Telecommun & Informat IEETA P-3810193 Aveiro Portugal

The paper shows that fast counting non-zero components (Hamming weights) and comparing the results (Hamming distances) in large sets of data items is important for numerous practical applications and this problem has been broadly investigated by software and hardware designers. It is frequently referenced as population or vector set bits count (or simply popcount). This paper is dedicated to multi-core FPGA-based accelerators that compute Hamming weights/distances and compare the results with fixed thresholds and variable bounds. It is shown that widely available in contemporary FPGAs digital signal processing slices may be used efficiently and they provide the fastest and the less resource consuming solutions. A thorough analysis and comparison with the best known alternatives both in hardware and in software is presented and supported by numerous experiments in the recent Nexys-4, ZedBoard and ZyBo prototyping systems. Complete hardware description language (VHDL) specifications for core components are given ready to be synthesized, implemented, tested and evaluated. Experiments with the proposed designs clearly demonstrate significant speed-up comparing to known hardware/software alternatives.

关键词： Hamming weight/population/vector setbits counter Hamming weight comparator field-programmable gate array Digital signal processing slice Hardware accelerator On-chip architecture

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Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2023年第4期16卷 1-28页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Inst Informat Fed Univ Rio Grande Do Sul 9500 Bento Gonc Alves Ave BR-91501970 Porto Alegre RS Brazil

Numerous approximate computing (AC) techniques have been developed to reduce the design costs in error-resilient application domains, such as signal and multimedia processing, data mining, machine learning, and computer vision, to trade-off computation accuracy with area and power savings or performance improvements. Selecting adequate techniques for each application and optimization target is complex but crucial for high-quality results. In this context, Approximate High-Level Synthesis (AHLS) tools have been proposed to alleviate the burden of hand-crafting approximate circuits by automating the exploitation of AC techniques. However, such tools are typically tied to a specific approximation technique or a difficult-to-extend set of techniques whose exploitation is not fully automated or steered by optimization targets. Therefore, available AHLS tools overlook the benefits of expanding the design space by mixing diverse approximation techniques toward meeting specific design objectives with minimum error. In this work, we propose an AHLS design methodology for FPGAs that automatically identifies efficient combinations of multiple approximation techniques for different applications and design constraints. Compared to single-technique approaches, decreases of up to 30% in mean squared error and absolute increases of up to 6.5% in percentage accuracy were obtained for a set of image, video, signal processing and machine learning benchmarks.

关键词： High-level synthesis approximate computing field-programmable gate array design space exploration

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A Comparison on Finite-Set Model Predictive Torque Control Schemes for PMSMs

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2018年第10期33卷 8838-8847页

作者： Sandre-Hernandez, Omar Rangel-Magdaleno, Jose Morales-Caporal, Roberto Natl Inst Astrophys Opt & Elect Dept Elect Puebla 72840 Mexico Technol Inst Apizaco Postgrad Studies & Res Div Tlaxcala 90300 Mexico

This paper introduces the comparison of four predictive torque control schemes for a permanent-magnet synchronous machine (PMSM). The first method is the finite-set model predictive control (FS-MPC). In FS-MPC, the optimal switching state is selected based on the evaluation and minimization of a cost function for all possible voltage space vectors (VSVs) of the inverter. The second method performs a simplified FS-MPC where the selection and evaluation of the possible VSVs are reduced to only three. The third method is based on the principle of predictive direct torque control (PDTC), where the duty cycle of the switching state is optimized for application in the inverter. Finally, a method that combines FS-MPC and PDTC named model predictive torque control is presented. This paper introduces the methodology and the results of a comprehensive comparison of the four predictive schemes based on different criterions. The control schemes are implemented on a field-programmable gate array and are applied to a PMSM. Experimental results are presented to validate the presented comparison and discussion.

关键词： field-programmable gate array permanent-magnet synchronous machine (PMSM) predictive control torque control

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programmable active memories: Reconfigurable systems come of age

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1996年第1期4卷 56-69页

作者： Vuillemin, JE Bertin, P Roncin, D Shand, M Touati, HH Boucard, P INRIA F-78150 ROCQUENCOURT FRANCE

programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAM's offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAM's, through the example of DECPeRLe-1, an experimental device built in 1992. PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions;no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in 1992. A technology shrink increases the performance gap between conventional processors and PAM's. By Noyce's law, we predict by how much the performance gap will widen with time.

关键词： programmable active memory PAM reconfigurable system field-programmable gate array FPGA

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