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programmable active memories: Reconfigurable systems come of age

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1996年第1期4卷 56-69页

作者： Vuillemin, JE Bertin, P Roncin, D Shand, M Touati, HH Boucard, P INRIA F-78150 ROCQUENCOURT FRANCE

programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAM's offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAM's, through the example of DECPeRLe-1, an experimental device built in 1992. PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions;no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in 1992. A technology shrink increases the performance gap between conventional processors and PAM's. By Noyce's law, we predict by how much the performance gap will widen with time.

关键词： programmable active memory PAM reconfigurable system field-programmable gate array FPGA

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Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2017年 874卷 50-56页

作者： Sano, Y. Horii, Y. Ikeno, M. Sasaki, O. Tomoto, M. Uchida, T. Nagoya Univ Chikusa Ku Nagoya Aichi 4648602 Japan High Energy Accelerator Res Org KEK Tsukuba Ibaraki 3050801 Japan

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Time-to-digital converter field-programmable gate array

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ION-FAST as the NIRFI's Ionospheric Diagnostic Platform

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ATMOSPHERE 2024年第2期15卷 188页

作者： Moiseev, Sergey P. Shindin, Alexei V. Grekhneva, Kseniya K. Pavlova, Viktoriya A. Timukin, Nikita S. Lobachevsky State Univ Nizhni Novgorod Radiophys Res Inst Bolshaya Pecherskaya St 25-12a Nizhnii Novgorod 603950 Russia

In December 2021, we presented a prototype of a fast ionosonde for vertical sounding based on the usage of publicly available radio-electronic components. This approach led to a major reduction in the cost of the created device. We called our development ION-FAST, which characterizes the key feature of the ionosonde: the possibility of continuous operation at a speed of one ionogram per second, which is required to study the rapid processes of redistribution of the electron concentration during heating experiments. In May 2022, an ionosonde for vertical sounding of the ionosphere, developed at the Radiophysical Research Institute of Nizhni Novgorod (NIRFI), was put into continuous operation at the SURA facility. This report provides a description of the improvements made to the prototype over the last year and the path to be passed from idea to implementation. The results of the first months of the prototype's operation (especially the results of the supporting optic experiment in August 2022), as well as prospects for further use and modernization, are provided. In addition, the realization of the oblique chirp-sounding receiver prototype as an extension of the proposed diagnostic platform's functionality, including the first results, is presented.

关键词： ionosonde ionosphere field-programmable gate array software-defined radio vertical sounding oblique sounding ionogram

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FPGAS VERSUS GPUS IN DATACENTERS

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IEEE MICRO 2017年第1期37卷 60-72页

作者： Falsafi, Babak Dally, Bill Singh, Desh Chiou, Derek Yi, Joshua J. Sendag, Resit Ecole Polytech Fed Lausanne Dept Comp & Commun Sci Lausanne Switzerland Stanford Univ Comp Sci & Elect Engn Stanford CA 94305 USA Amazon Software Dev Toronto ON Canada Microsoft Redmond WA USA Dechert Philadelphia PA USA Univ Rhode Isl Elect & Comp Engn Kingston RI 02881 USA

THIS ARTICLE PRESENTS POSITION STATEMENTS AND A QUESTION-AND-ANSWER SESSION BY PANELISTS AT THE FOURTH WORKSHOP ON COMPUTER ARCHITECTURE RESEARCH DIRECTIONS. THE SUBJECT OF THE DEBATE WAS THE USE OF field-programmable... 详细信息

关键词： Bandwidth allocation CARD computer architecture Data centers datacenter debate field programmable gate arrays field-programmable gate array FPGA GPU Graphics processing units Programming research directions Servers

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An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking

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MICROELECTRONICS JOURNAL 2014年第6期45卷 690-701页

作者： Xin, Yao Li, Will X. Y. Cheung, Ray C. C. Chan, Rosa H. M. Yan, Hong Song, Dong Berger, Theodore W. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ So Calif Ctr Neural Engn Dept Biomed Engn Los Angeles CA 90089 USA

Recent studies have verified the efficiency of stochastic state point process filter (SSPPF) in coefficients tracking in the modeling of the mammalian nervous system. In this study, a hardware architecture of SSPPF is both designed and implemented on a field-programmable gate array (FPGA). It provides a time-efficient method to investigate the nonlinear neural dynamics through coefficients tracking of a generalized Laguerre-Volterra model describing the spike train transformations of different brain sub-regions. The proposed architecture is able to process matrices and vectors with arbitrary sizes. It is designed to be scalable in parallel degree and to provide different customizable levels of parallelism, by exploring the intrinsic parallelism of the FPGA. Multiple architectures with different degrees of parallelism are explored. This design maintains numerical precision and the proposed parallel architectures for coefficients estimation are also much more power efficient. (C) 2014 Elsevier Ltd. All rights reserved.

关键词： SSPPF Adaptive filter Neural modeling field-programmable gate array

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Fully parallel low-density parity-check code-based polar decoder architecture for 5G wireless communications

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ETRI JOURNAL 2024年第3期46卷 485-500页

作者： Devadoss, Dinesh Kumar Ramapackiam, Shantha Selvakumari Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi India

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10-4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

关键词： 5G new radio belief propagation field-programmable gate array low-density parity-check code pipeline polar code

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Low-Complexity Square-Root Unscented Kalman Filter Design Methodology

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2023年第11期42卷 6900-6928页

作者： Dutt, Rashi Acharyya, Amit Indian Inst Technol Hyderabad Dept Elect Engn Hyderabad 502285 Telangana India

Square-root unscented Kalman filter (SRUKF) is a widely used state estimator for several state of-the-art, highly nonlinear, and critical applications. It improves the stability and numerical accuracy of the system compared to the non-square root formulation, the unscented Kalman filter (UKF). At the same time, SRUKF is less computationally intensive compared to UKF, making it suitable for portable and battery-powered applications. This paper proposes a low-complexity and power-efficient architecture design methodology for SRUKF presented with a use case of the simultaneous localization and mapping (SLAM) problem. Implementation results show that the proposed SRUKF methodology is highly stable and achieves higher accuracy than the extensively used extended Kalman filter and UKF when developed for highly critical nonlinear applications such as SLAM. The design is synthesized and implemented on resource constraint Zynq-7000 XC7Z020 FPGA-based Zedboard development kit and compared with the state-of-the-art Kalman filter-based FPGA designs. Synthesis results show that the architecture is highly stable and has significant computation savings in DSP cores and clock cycles. The power consumption was reduced by 64% compared to the state-ofthe-art UKF design methodology. ASIC design was synthesized using UMC 90-nm technology, and the results for on-chip area and power consumption results have been discussed.

关键词： Square-root unscented Kalman filter Low-complexity VLSI architecture Householder coordinate rotation digital computer (CORDIC) field-programmable gate array ASIC SLAM

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A REprogrammable gate array AND APPLICATIONS

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PROCEEDINGS OF THE IEEE 1993年第7期81卷 1030-1041页

作者： TRIMBERGER, S Xilinx Inc. San Jose CA

A field programmable gate array (FPGA) can implement thousands of gates of logic, has no up-front fixed costs, and can be programmed in a few minutes by users at their site. This paper describes an FPGA that is programmed by writing into on-chip static memory. This kind of FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation. Reprogrammable technology allows software-like design methodologies to be applied to logic design. This paper describes the construction of this kind of FPGA, design tradeoffs and examples of applications that take advantage of reprogrammability.

关键词： FPGA PLD programming application specific integrated circuits circuit layout CAD field-programmable gate array logic CAD logic arrays logic design on-chip static memory reprogrammable gate array

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A TIME-DOMAIN PULSE AMPLITUDE AND WIDTH DISCRIMINATION METHOD FOR PHOTON COUNTING

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METROLOGY AND MEASUREMENT SYSTEMS 2018年第2期25卷 269-282页

作者： del Mar Correa, Maryam Perez, Freddy R. Univ Pondficia Bolivariana Ctr Ciencia Basica Grp Opt & Espect Circular 1 70-01 Medellin Colombia

This work shows a time-domain method for the discrimination and digitization of parameters of voltage pulses coming from optical detectors, taking into account the presence of electronic noise and afterpulsing. Our scheme is based on an FPGA-based time-to-digital converter as well as an adjustable-threshold comparator complemented with commercial elements. Here, the design, implementation and optimization of a multiphase TDC using delay lines shorter than a single clock period is also described. The performance of this signal processing system is discussed through the results from the statistical code density test, statistical distributions of measurements and information gathered from an optical detector. Unlike dual voltage threshold discriminators or constant-fraction discriminators, the proposed method uses amplitude and time information to define an adjustable discrimination window that enables the acquisition of spectra.

关键词： field-programmable gate array time-to-digital converter spectroscopy photomultiplier photon counting discriminator after-pulsing low-voltage differential signalling

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FPGA-based adaptive backstepping control system using RBFN for linear induction motor drive

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IET ELECTRIC POWER APPLICATIONS 2008年第6期2卷 325-340页

作者： Lin, F. -J. Teng, L. -T. Chen, C. -Y. Hung, Y. -C. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan Natl Dong Hwa Univ Dept Elect Engn Hualien 974 Taiwan

A field-programmable gate array (FPGA)-based adaptive backstepping control system with radial basis function network (RBFN) observer is proposed to control the mover position of a linear induction motor (LIM). First, the indirect. field-oriented mechanism is adopted for controlling the LIM. Next, a backstepping control law is designed step by step for the tracking control of periodic reference trajectories, in which the uncertainties are lumped by a conservative constant. However, the lumped uncertainty is unknown and difficult to obtain in advance in practical applications. Therefore an RBFN is derived to observe the lumped uncertainty in real-time, and an adaptive backstepping control system with RBFN observer is resulted. Then, an FPGA chip is adopted to implement the indirect. field-oriented mechanism and the developed control algorithms for possible low-cost, high-performance industrial applications. The effectiveness of the proposed control scheme is verified by some simulated and experimental results. By using the adaptive backstepping control system with RBFN observer, the FPGA-based LIM drive possesses the advantages of good transient control performance and robustness to uncertainties in the tracking of periodic reference trajectories.

关键词： induction motor drives radial basis function network periodic reference trajectory tracking radial basis function networks RBFN observer observers field-programmable gate array indirect field-oriented control lumped uncertainty neurocontrollers mover position control field programmable gate arrays linear induction motor drive adaptive control linear induction motors FPGA machine vector control adaptive backstepping control position control transient control performance

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