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Implementation and co-simulation based on FPGA of circulating currents control in MMC using reduced order generalized integrator

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ELECTRICAL ENGINEERING 2020年第3期102卷 1531-1547页

作者： Atoui, Elmoatez Billah Mesbah, Tarek Atoui, Hamza Kelaiaia, Samia Badji Mokhtar Univ Dept Elect Engn Annaba Algeria Badji Mokhtar Univ Dept Elect Annaba Algeria

One of the major issues concerning the MMC is the control of circulating currents. Through the elimination of even-order harmonic currents superimposed on the DC component, the MMC stress and losses can be reduced which leads to an increase of its lifetime. This paper proposes a new circulating current controller based on reduced order generalized integrator implemented in the stationary alpha beta reference frame;intended to eliminate the second-order harmonic current for both three-phase and single-phase systems without a need for any measurement or estimation of the DC component contained in the circulating currents. Also, the whole digital architecture of the proposed controller is designed using hardware description language and implemented on Digilent Atlys-Xilinx Spartan-6 FPGA board. The validity and effectiveness of the proposed control strategy have been verified for both continuous-time and discrete-time domains through a set of simulations and FPGA-based co-simulation.

关键词： Modular multilevel converter field-programmable gate array VSC-HVDC system Renewable energy

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FPGA Implementation of Rate-Adaptable Prefix-Free Code Distribution Matching for Probabilistic Constellation Shaping

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2021年第4期39卷 1072-1080页

作者： Yu, Qinyang Corteselli, Steve Cho, Junho Nokia Bell Labs Holmdel NJ 07733 USA Shanghai Univ Key Lab Specialty Fiber Opt & Opt Access Networks Shanghai 200444 Peoples R China

In this work, we implement a rate-adaptable (RA) prefix-free code distribution matching (PCDM) encoder in a field-programmable gate array (FPGA). The implemented RA-PCDM encoder supports a wide range of information rates from 1.6 to 4.8 bit/symbol with fine granularity of 0.2 bit/symbol in probabilistic constellation shaping (PCS) systems. The shaping performance of the implemented RA-PCDM is within 0.55 dB of the theoretical limit. Massively parallel encoding of RA-PCDM is demonstrated using a sliding window processor, in a universal architecture for all PCDM codebooks. Given that the procedure and complexity of RA-PCDM decoding is almost the same as those of RA-PCDM encoding, it is shown that the RA-PCDM uses substantially less hardware area than a traditional rate adaptation scheme based on low-density parity-check (LDPC) codes, while offering finer rate granularity and shaping gain. The RA-PCDM is therefore a practical PCS technology that enables high-throughput optical communications to approach channel capacity more closely at a lower cost than RA-LDPC.

关键词： Encoding Forward error correction Probabilistic logic Parity check codes field programmable gate arrays Quadrature amplitude modulation Standards field-programmable gate array optical fiber communication prefix-free code distribution matching probabilistic constellation shaping

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Real-time FPGA Integration for ECG Monitoring: Bidirectional Recurrent Chimp Search Model

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IETE JOURNAL OF RESEARCH 2024年第8期70卷 6848-6863页

作者： Shanthi, K. G. Kinol, A. Mary Joy Santhi, S. Kannan, K. RMK Coll Engn & Technol Dept Elect & Commun Engn Chennai Tamil Nadu India Saveetha Univ Saveetha Inst Med & Tech Sci Saveetha Sch Engn Dept Elect & Commun Engn Chennai Tamil Nadu India KIT Kalaignarkarunanidhi Inst Technol Dept Comp Sci & Engn Coimbatore Tamil Nadu India

The primary diagnostic tool for monitoring problems with the heart or related diseases is the electrocardiogram (ECG). The rising mortality rate caused by cardiac abnormalities leads to the development of more advanced techniques to detect heart anomalies are is of paramount importance. An electrocardiogram (ECG) is used for multiple diagnostic purposes since it produces continuous tracings of the electrophysiological activity generated from the heart. This paper developed a Bidirectional recurrent chimp search (Bi-RCS) method for diagnosing abnormalities by collecting ECG signals via various phases such as the data acquisition phase, signal processing phase, feature extraction phase, abnormality detection phase, real-time FPGA integration phase, monitoring and reporting phase as well as feedback phase. Signal pre-processing removes contaminants like noise using the Adaptive filtering methodology which severely limits the utility of the recorded ECG for better clinical evaluation. Bi-RNN is utilized for extracting related features and detecting abnormalities and the Chimp search optimization is employed to tune the parameters of Bi-RNN. After detecting the abnormalities, the reports of patients are monitored and recorded to provide an alert signal to healthcare providers. Finally, the potency of the methodology is analyzed with the ECG signal dataset and metrics like precision, F1-score accuracy, sensitivity, and specificity values. The obtained outputs equalized with the existing methods like KNN, EBT, and SVM. The analysis showed convincing performance with an accuracy of 99% and less error rate of 0.05.

关键词： Adaptive filtering Bidirectional Recurrent Neural Network Chimps optimization Electrocardiogram field-programmable gate array

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Fault section estimation for distribution substations using on-chip design

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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 2012年第6期35卷 675-685页

作者： Chen, Wen-Hui Li, Chao-Tang Natl Taipei Univ Technol Grad Inst Automat Technol Taipei 106 Taiwan

A new fault detection circuit for on-chip design is presented in this article. The circuit function to detect substation faults has been investigated and verified on an Altera DE1 platform with Cyclone II 2C20 field-programmable gate array. The experimental results showed that the hardware prototyping is feasible for practical applications. Compared to existing fault diagnosis methods, the proposed hardware implementation is more suitable for real-time applications as it is able to achieve high-speed inference. Additionally, the computational burden on host computers in a supervisory control and data acquisition system can thus be reduced through the presented framework.

关键词： field-programmable gate array power SCADA systems fault diagnosis

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Design and FPGA implementation of lattice wave digital notch filter with minimal transient duration

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IET SIGNAL PROCESSING 2020年第7期14卷 440-447页

作者： Sharma, Abhay Kumar Rawat, Tarun Agrawal, Anjali Univ Delhi Fac Technol New Delhi India

In this study, the design and field-programmable gate array (FPGA) implementation of the digital notch filter with the lattice wave digital filter (LWDF) structure is presented. For reducing the initial signal transient, the variable notch bandwidth filter is designed. During the initial samples, the notch filter has a wide bandwidth in order to diminish signal transient. As time moves forward, the notch bandwidth reduces to attain the possible minimum width. This results in minimised transient duration notch filter with a sufficiently high-quality factor. Previously, the IIR structure has been used for implementing the time varying bandwidth notch filter. Such a filter requires two variable coefficients for varying the notch width with time. The advantage of using a LWDF structure is that only one coefficient has variable values to vary the notch width with time. Therefore, the number of memory locations required to implement the proposed design is reduced by half. Moreover, the LWDF is less sensitive to the word-length effects. Thus, the proposed lattice wave digital notch filter (LWDNF) produces better results compared to the existing literature in terms of error analysis. The suggested LWDNF is then implemented on a field-programmable gate array using a Xilinx system generator for the DSP design suite.

关键词： wave digital filters error analysis notch filters field programmable gate arrays logic design Q-factor minimal transient duration field-programmable gate array lattice wave digital filter structure signal transient variable notch bandwidth filter time-varying bandwidth notch filter notch width lattice wave digital notch filter FPGA quality factor infinite impulse response structure minimised transient duration error analysis field programmable gate array Xilinx system generator DSP design suite

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Scalable On-Chip Optoelectronic Ising Machine Utilizing Thin-Film Lithium Niobate Photonics

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ACS PHOTONICS 2024年第4期11卷 1703-1714页

作者： Li, Zhenhua Gan, Ranfeng Chen, Zihao Deng, Zhaoang Gao, Ran Chen, Kaixuan Guo, Changjian Zhang, Yanfeng Liu, Liu Yu, Siyuan Liu, Jie Sun Yat Sen Univ Sch Elect & Informat Technol State Key Lab Optoelect Mat & Technol Guangzhou 510006 Peoples R China Beijing Inst Technol Sch Informat & Elect Beijing 100081 Peoples R China South China Normal Univ South China Acad Adv Optoelect Guangdong Prov Key Lab Opt Informat Mat & Technol Guangzhou 510006 Peoples R China Hefei Natl Lab Hefei 230088 Peoples R China Zhejiang Univ Coll Opt Sci & Engn Int Res Ctr Adv Photon State Key Lab Extreme Photon & Instrumentat Hangzhou 310058 Peoples R China Zhejiang Univ Jiaxing Res Inst Intelligent Opt & Photon Res Ctr Jiaxing Key Lab Photon Sensing & Intelligent Imagi Jiaxing 314000 Peoples R China

The Ising machine (IM) has emerged as a promising tool for tackling nondeterministic polynomial-time hard combinatorial optimization problems in real-world applications. Among various types of IMs, optoelectronic IMs based on electro-optical (EO) modulators stand out as an impressive platform for Ising computations. They offer a simple and stable architecture, with the EO modulator providing a natural inline nonlinear transfer function for the Ising model. However, integrated optoelectronic IMs have not been demonstrated until now, and exploring large-scale computations within the constraints of digital hardware resources remains an open challenge for these systems. In this paper, an integrated optoelectronic IM based on a thin-film lithium niobate (TFLN) photonic chip is presented, in conjunction with a sparse matrix-vector multiplication algorithm embedded in a field-programmable gate array that optimizes hardware resource utilization and minimizes computational latency. This setup allows us to solve multiple types of MAX-CUT problems with up to 2048 spins and achieve a remarkably low iteration latency of 1.78 mu s. To further address the constraints posed by digital devices when tackling larger-scale Ising problems, we extend the application of the TFLN chip to yet another new scheme in which the single, compact on-chip modulator concurrently performs operations of linear multiplication and nonlinear transformation. This scheme demonstrates the capability to address large-scale MAX-CUT problems involving up to 16,384 spins, which, to the best of our knowledge, are the largest-scale problems solved on an on-chip IM, highlighting its potential to overcome digital limitations. The TFLN-based optoelectronic IMs provide a compact solution with high scalability for potentially practical applications in addressing complex combinatorial optimization problems.

关键词： Ising machine optical computing thin-filmlithium niobate field-programmable gate array matrix-vector multiplication nonlinear operation

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Low-power DSSS transmitter and its VLSI implementation

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ANNALS OF TELECOMMUNICATIONS 2021年第7-8期76卷 537-543页

作者： Jayasanthi, M. Kalaivani, R. PSG Inst Technol & Appl Res Dept ECE Coimbatore Tamil Nadu India Erode Sengunthar Engn Coll Dept ECE Erode India

An interesting area of application in wireless data communication is direct-sequence spread spectrum (DSSS). Spread spectrum communication techniques make the signals more robust against interference and jamming. These are based on a concept that narrowband signal is scrambled before transmission in such a way that the signals occupy a much larger part of the radio frequency spectrum. As the digital and the analogue system components are required on the same substrate in today's mixed-signal chips, the DSSS transmitter system is proposed to be implemented in field-programmable gate array (FPGA)-based platforms and application-specific integrated circuits (ASICs). With a low-power very large-scale integration (VLSI) architecture, sophisticated processing of wide-bandwidth DSSS systems can be exploited in FPGAs/ASICs. In this article, binary pseudo-noise (PN) sequences are generated using a low-power linear feedback shift register (LFSR) in order to spread transmit signals extensively. The proposed low-power design of LFSR and DSSS transmitter with implementation results is illustrated in this paper. Dynamic power dissipation of the proposed DSSS transmitter is reduced up to 15% and 15.6% when compared to the conventional LFSR and the Gold code-based systems respectively. The proposed hardware is implemented in 180-nm technology and operates at 15.36-MHz frequency.

关键词： Latches Linear feedback shift register Low-power DSSS transmitter Spread spectrum communication field-programmable gate array

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Gating function based on transmission delays and stochastic resonance in motif network with FPGA implementation

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NONLINEAR DYNAMICS 2022年第3期108卷 2731-2749页

作者： Hu, Zhicai Wang, Jiang Hao, Xinyu Li, Kai Tianjin Univ Sch Elect & Informat Engn Tianjin 30072 Peoples R China

Attuned function of different brain regions relies on the precise yet flexible communication between their subsystems, and flexible gating of information flow among brain motif network could increase neuronal response which is selected. However, the underlying mechanism remains to be investigated. In this paper, we present a hardware efficient, scalable, and real-time computing strategy for the implementation of large-scale motif cortical network via field-programmable gate array (FPGA). Based on FPGA network model, we explore the information transmission in cortical network by investigating the gating function from the perspective of stochastic resonance, which is an important way for neuronal population to communicate. Remarkably, it is found that the cortical network can only transmit signal when the excitatory-inhibitory (E/I) balance is lopsided, which is called as "E/I semi-balanced state." Moreover, time delay between populations affects the information transmission mainly by determining the phase timestamp at which the signal is transmitted from one region to another. In short, E/I semi-balance and time delay together realize the gating function to input in cortical motif network. The experimental results demonstrate that the gating function of information is determined by E/I semi-balance and time delay in cortical motif network. Besides, mean-field theory is applied to verify the simulation results, and the cortical network is found to resonate in the form of cycle dynamics. Verification result shows that the simulation speed on hardware is 27.4 ms, which is much better than the 90 s on MATLAB. Consequently, the hardware synthesis results indicate high computational speed and low area utilization, which helps to deploy the function realization of biological neuronal network in intelligent control and remote communication.

关键词： Stochastic resonance Gating function field-programmable gate array Information transmission

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Hybrid analytical model of switched reluctance machine for real-time hardware-in-the-loop simulation

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IET ELECTRIC POWER APPLICATIONS 2017年第6期11卷 1114-1123页

作者： Xu, Fengqiu Dinavahi, Venkata Xu, Xianze Wuhan Univ Elect Informat Sch Wuhan Hubei Province Peoples R China Univ Alberta Dept Elect & Comp Engn 9107-116 St Edmonton AB T6G 2V4 Canada

Applications of switched reluctance machine (SRM) are increasing in the industry due to their many desirable features. This study proposes a hybrid analytical model (HAM) of the SRM for the hardware-in-the-loop (HIL) simulation. To obtain satisfactory accuracy, the phase flux linkage is solved by the magnetic equivalent circuit (MEC) method when the stator and rotor poles overlap, and by the space harmonic method (SHM) when the poles do not overlap. The backward Euler and Newton-Raphson methods are used to calculate the exciting current, while the Gaussian quadrature is used to compute the electromagnetic torque in the HIL simulation. The digital hardware implementation of computation components are developed on the field-programmable gate array by exploiting the parallel hardware architecture and fully pipelined arithmetic processing. To highlight the performance of the HAM, the captured real-time results are compared with the off-line transient solution obtained through the co-simulation of Ansys Maxwell((R)), Ansys Simplorer((R)), and Simulink((R)), which model the SRM, drive circuit, and control system, respectively.

关键词： reluctance machines hardware-in-the loop simulation electric machine analysis computing machine theory magnetic circuits magnetic flux equivalent circuits stators rotors harmonic analysis Newton-Raphson method Gaussian processes integration field programmable gate arrays parallel architectures pipeline arithmetic Ansys Simplorer simulation Simulink simulation drive circuit control system Ansys Maxwell simulation offline transient solution pipelined arithmetic processing parallel hardware architecture field-programmable gate array digital hardware implementation electromagnetic torque computation Gaussian quadrature exciting current calculation Newton-Raphson method backward Euler method SHM space harmonic method rotor pole stator pole MEC method magnetic equivalent circuit method phase flux linkage HIL simulation hybrid analytical model HAM SRM hardware-in-the-loop simulation switched reluctance machine

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The Implementation of an Amplitude-Locked Loop for Digital Communication Chip Design

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WIRELESS PERSONAL COMMUNICATIONS 2013年第4期72卷 2773-2801页

作者： Jong, Gwo-Jia Chen, Yin-Chih Huang, Chen-Shen Yu, Gwo-Jeng Horng, Gwo-Jiun Natl Kaohsiung Univ Appl Sci Inst Elect Engn Kaohsiung 807 Taiwan Cheng Shiu Univ Dept Comp Sci & Informat Engn Kaohsiung Taiwan Natl Cheng Kung Univ Dept Comp Sci & Informat Engn Tainan 70101 Taiwan

The purpose of a communication system is to transmit an information-bearing message signal through a channel that separates a transmitter from a receiver. The modulated carrier is often induced and interfered with by various noise sources. The co-channel separation system is a demodulation process function that operates at the same carrier modulation system. Here, we adopted the field-programmable gate array (FPGA) design platform configuration to develop, implement and achieve co-channel separation for an amplitude-locked loop demodulation chip-design digital system with additive white Gaussian noise interference. In this paper, the compact reconfigurable I/O built-in FPGA chip system is integrated and applied to obtain the cross-field relevant integration function for communication and chip-design system via programming in a graphical language. Additionally, the FPGA chip-design system runs all of the program code in hardware and provides high reliability and determinism. This cross-field ideal is adopted to save time and reduce complexity in the design development of a custom circuitry system. The FPGA chip-design system described in this paper is also used to achieve a digital communication chip prototype design model, followed by presentation of the steps necessary for building and program verification. The communication and chip-design concept may provide very useful physical applications for the industry.

关键词： Co-channel field-programmable gate array Additive white Gaussian noise Amplitude-locked loop LabVIEW Communication chip prototype design

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