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Fully parallel low-density parity-check code-based polar decoder architecture for 5G wireless communications

ETRI JOURNAL 2024年第3期46卷 485-500页

作者： Devadoss, Dinesh Kumar Ramapackiam, Shantha Selvakumari Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi India

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10-4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

关键词： 5G new radio belief propagation field-programmable gate array low-density parity-check code pipeline polar code

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An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking

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MICROELECTRONICS JOURNAL 2014年第6期45卷 690-701页

作者： Xin, Yao Li, Will X. Y. Cheung, Ray C. C. Chan, Rosa H. M. Yan, Hong Song, Dong Berger, Theodore W. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ So Calif Ctr Neural Engn Dept Biomed Engn Los Angeles CA 90089 USA

Recent studies have verified the efficiency of stochastic state point process filter (SSPPF) in coefficients tracking in the modeling of the mammalian nervous system. In this study, a hardware architecture of SSPPF is both designed and implemented on a field-programmable gate array (FPGA). It provides a time-efficient method to investigate the nonlinear neural dynamics through coefficients tracking of a generalized Laguerre-Volterra model describing the spike train transformations of different brain sub-regions. The proposed architecture is able to process matrices and vectors with arbitrary sizes. It is designed to be scalable in parallel degree and to provide different customizable levels of parallelism, by exploring the intrinsic parallelism of the FPGA. Multiple architectures with different degrees of parallelism are explored. This design maintains numerical precision and the proposed parallel architectures for coefficients estimation are also much more power efficient. (C) 2014 Elsevier Ltd. All rights reserved.

关键词： SSPPF Adaptive filter Neural modeling field-programmable gate array

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Modulation technique for series-connected H-bridge multilevel converters with equal load sharing

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IET POWER ELECTRONICS 2009年第3期2卷 275-286页

作者： Naumanen, V. Luukko, J. Itkonen, T. Pyrhonen, O. Pyrhonen, J. Lappeenranta Univ Technol Dept Elect Engn Lappeenranta Finland

An improved duty-cycle modulation scheme for multilevel inverters is introduced. The scheme exploits two-to-three axis coordinate transformation to achieve duty-cycles of each phase directly from the location of the reference vector in the Cartesian coordinate system. There is no need for trigonometric functions, which makes the applicability of the algorithm very good in a digital signal processor or a field-programmable gate array. The method also guarantees a low common-mode voltage output, because a zero-component is added only when operating at a voltage amplitude larger than 75% of the maximum amplitude of the reference vector The selection of zero-component is also simple and mathematically easy. The pulse-formation is formulated in such a way that the modules of the inverter are equally loaded, and the balance of the individual DC link voltages is maintained throughout the voltage region. The methods are verified with simulations and experimental tests on a seven-level 100 kVA, 3 kV prototype induction motor drive.

关键词： inverter Logic circuits series-connected H-bridge multilevel converter duty-cycle modulation scheme load sharing invertors low common-mode voltage output Microprocessors and microcomputers voltage 3 kV field programmable gate arrays field-programmable gate array apparent power 100 kVA power convertors trigonometric functions Power convertors and power supplies to apparatus digital signal processor induction motor drive individual DC link voltages digital signal processing chips Cartesian coordinate system axis coordinate transformation

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Self-reconfigurable approach for computation-intensive motion estimation algorithm in H.264/AVC

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OPTICAL ENGINEERING 2012年第4期51卷

作者： Lee, Jooheung Ryu, Chul Kim, Soontae Hongik Univ Dept Elect & Elect Engn Yeongi 339701 Chungnam South Korea Dongguk Univ Seoul Dept Informat & Commun Engn Seoul 100715 South Korea Korea Adv Inst Sci & Technol Dept Comp Sci Taejon 305701 South Korea

The authors propose a self-reconfigurable approach to perform H.264/AVC variable block size motion estimation computation on field-programmable gate arrays. We use dynamic partial reconfiguration to change the hardware architecture of motion estimation during run-time. Hardware adaptation to meet the real-time computing requirements for the given video resolutions and frame rates is performed through self-reconfiguration. An embedded processor is used to control the reconfiguration of partial bitstreams of motion estimation adaptively. The partial bitstreams for different motion estimation computation arrays are compressed using LZSS algorithm. On-chip BlockRAM is used as a cache to pre-store the partial bitstreams so that run-time reconfiguration can be fully utilized. We designed a hardware module to fetch the pre-stored partial bitstream from BlockRAM to an internal configuration access port. Comparison results show that our motion estimation architecture improves toward data reuse, and the memory bandwidth overhead is reduced. Using our self-reconfigurable platform, the reconfiguration overhead can be removed and 367 MB/sec reconfiguration rate can be achieved. The experimental results show that the external memory accesses are reduced by 62.4% and it can operate at a frequency of 91.7 MHz. (C) 2012 Society of Photo-Optical Instrumentation Engineers (SPIE). [DOI: 10.1117/***.51.4.047008]

关键词： bitstream compression configuration speed dynamic partial reconfiguration field-programmable gate array motion estimation

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Algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures

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IET SIGNAL PROCESSING 2018年第7期12卷 857-867页

作者： Poczekajlo, Pawel Wawryn, Krzysztof Koszalin Univ Technol Fac Elect & Comp Sci PL-75453 Koszalin Poland

A novel algorithm for the realisation of an orthogonal digital system performing three-dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state-space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field-programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct-form structure consisting of adders, multipliers, and delay elements.

关键词： FIR filters transfer functions field programmable gate arrays pipeline processing parameter analysis pipelined separable 3D finite impulse response filter Givens rotation structure orthogonal digital system three-dimensional filtering separable transfer function state-space approach coordinate rotation digital computer algorithm field-programmable gate array FPGA chip occupation

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SIKE'd Up: Fast Hardware Architectures for Supersingular Isogeny Key Encapsulation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第12期67卷 4842-4854页

作者： Koziel, Brian Ackie, A-Bon Khatib, Rami El Azarderakhsh, Reza Kermani, Mehran Mozaffari Florida Atlantic Univ CEECS Dept Boca Raton FL 33431 USA Univ S Florida CSE Dept Tampa FL 33620 USA

In this work, we present a fast parallel architecture to perform supersingular isogeny key encapsulation (SIKE). We propose and implement a fast isogeny accelerator architecture that uses fast and parallelized isogeny formulas. On top of our isogeny accelerator, we build a novel architecture for the SIKE primitive, which provides both quantum and IND-CCA security. We synthesized this architecture on the Xilinx Artix-7, Virtex-7, and Kintex UltraScale+ FPGA families. Over Virtex-7 FPGA's, our constant-time implementations are roughly 14% faster than the state-of-the-art with a better area-time product. At the NIST security level 5 on a Kintex UltraScale+ FPGA, we can execute the entire SIKE protocol in 15.3 ms. This work continues to improve the speed of isogeny-based computations and also features all parameter sets of the SIKE round 2 specification, with results applicable to NIST's post-quantum standardization process.

关键词： Elliptic curves NIST field programmable gate arrays Public key Computer architecture field-programmable gate array isogeny-based cryptography post-quantum cryptography SIKE

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Evolutionary design of hash function pairs for network filters

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APPLIED SOFT COMPUTING 2017年 56卷 173-181页

作者： Dobai, Roland Korenek, Jan Sekanina, Lukas Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat Brno Czech Republic

Network filtering is a challenging area in high-speed computer networks, mostly because lots of filtering rules are required and there is only a limited time available for matching these rules. Therefore, network filters accelerated by field-programmable gate arrays (FPGAs) are becoming common where the fast lookup of filtering rules is achieved by the use of hash tables. It is desirable to be able to fill-up these tables efficiently, i.e. to achieve a high table-load factor in order to reduce the offline time of the network filter due to rehashing and/or table replacement. A parallel reconfigurable hash function tuned by an evolutionary algorithm (EA) is proposed in this paper for Internet Protocol (IP) address filtering in FPGAs. The EA fine-tunes the reconfigurable hash function for a given set of IP addresses. The experiments demonstrate that the proposed hash function provides high-speed lookup and achieves a higher table-load factor in comparison with conventional solutions. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Evolutionary algorithm Hash function Network filter field-programmable gate array Cuckoo

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Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

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IEEE MICRO 2017年第5期37卷 44-51页

作者： Tokusashi, Yuta Matsutani, Hiroki Keio Univ Tokyo Japan Keio Univ Dept Informat & Comp Sci Tokyo Japan

Key-value store accelerators based on field-programmable gate arrays (FPGAs) have been proposed to achieve higher performance per watt than software-based processing. However, both their cache capacity and application domains are limited. The authors' proposed multilevel NoSQL cache architecture utilizes both an FPGA-based hardware cache and a complementary in-kernel software cache. Their design reduces the cache miss ratio and improves throughput compared to the nonhierarchical design.

关键词： Accelerators field programmable gate arrays field-programmable gate array FPGA key-value store NoSQL Random access memory

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Very large scale integration implementation of seizure detection system with on-chip support vector machine classifier

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IET CIRCUITS DEVICES & SYSTEMS 2022年第1期16卷 1-12页

作者： Shanmugam, Shalini Dharmar, Selvathi Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi Tamil Nadu India

Epilepsy is one of the most common neurological disorders;it affects millions of people globally. Because of the risks to health that it causes, the study and analysis of epilepsy have been given considerable attention in the biomedical field. In a neurological diagnosis, an automated device for detecting seizures or epilepsy from an electroencephalogram (EEG) signal has a significant role. This research work proposes a very large scale integration implementation system for the automatic detection of seizures. Before classification, feature extraction was performed by discrete wavelet transform (DWT) and on-chip classification was performed by a linear support vector machine. The polyphase architecture of Daubechies fourth-order wavelet three-level DWT was used to minimize computational time. The systolic array architecture-based support vector machine classifier using parallel processing helps to minimize the computational complexity of the proposed method. This research work uses an open access EEG dataset. Hardware implementation was done on a field-programmable gate array (FPGA). Efficient results were produced compared with the existing system on chip (SoC) and FPGA seizure detection systems.

关键词： on-chip classification medical signal processing neurophysiology epilepsy systolic arrays scale integration implementation system feature extraction automatic detection polyphase architecture hardware implementation signal classification medical disorders computational time common neurological disorders biomedical field linear support vector machine field-programmable gate array on-chip support vector machine classifier seizure detection system electroencephalogram signal neurological diagnosis medical signal detection support vector machines automated device field programmable gate arrays systolic array architecture-based support vector machine classifier Daubechies fourth-order wavelet three-level DWT electroencephalography wavelet transforms discrete wavelet transforms

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Acceleration of FPGA Based Convolutional Neural Network for Human Activity Classification Using Millimeter-Wave Radar

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IEEE ACCESS 2019年 7卷 88917-88926页

作者： Lei, Peng Liang, Jiawei Guan, Zhenyu Wang, Jun Zheng, Tong Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China Beihang Univ Sch Cyber Sci & Technol Beijing 100191 Peoples R China

Deep learning techniques have attracted much attention in the radar automatic target recognition. In this paper, we investigate an acceleration method of the convolutional neural network (CNN) on the field-programmable gate array (FPGA) for the embedded application of the millimeter-wave (mmW) radar-based human activity classification. Considering the micro-Doppler effect caused by a person's body movements, the spectrogram of mmW radar echoes is adopted as the CNN input. After that, according to the CNN architecture and the properties of the FPGA implementation, several parallel processing strategies are designed as well as data quantization and optimization of classification decision to accelerate the CNN execution. Finally, comparative experiments and discussions are carried out based on a measured dataset of nine individuals with four different actions by using a 77-GHz mmW radar. The results show that the proposed method not only maintains the high classification accuracy but also improves its execution speed, memory requirement, and power consumption. Specifically, compared with the implementation of the same network model on a graphics processing unit, it could achieve the speedup of about 30.42% at the cost of the classification accuracy loss of only 0.27%.

关键词： Human activity classification millimeter-wave radar convolutional neural network field-programmable gate array acceleration

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