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IEEE MICRO 2017年第3期37卷 52-61页

作者： Caulfield, Adrian M. Chung, Eric S. Putnam, Andrew Angepat, Hari Firestone, Daniel Fowers, Jeremy Haselman, Michael Heil, Stephen Humphrey, Matt Kaur, Puneet Kim, Joo-Young Lo, Daniel Massengill, Todd Ovtcharov, Kalin Papamichael, Michael Woods, Lisa Lanka, Sitaram Chiou, Derek Burger, Doug Microsoft Redmond WA 98052 USA Microsoft Azure Networking Host SDN Team Redmond WA 98052 USA

The Configurable Cloud datacenter architecture introduces a layer of reconfigurable logic between the network switches and servers. The authors deploy the architecture over a production server bed and show how it can accelerate applications that were explicitly ported to field-programmable gate arrays, support hardware-first services, and accelerate applications without any application-specific FPGA code being written.

关键词： accelerators datacenter distributed computing field-programmable gate array FPGA hyperscale

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Asynchronous control and driver for high-speed LED display with local scanning approach

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IET CIRCUITS DEVICES & SYSTEMS 2020年第1期14卷 1-6页

作者： Hsia, Shih-Chang Lin, Yu-Cheng Wong, Wing-Kwong Hsu, Ren-Chien Natl Yunlin Univ Sci & Technol Dept Elect 123 Univ RdSect 3 Touliu Taiwan

This study presents an extendable full-colour light emitting diode (LED) display based on field-programmable gate array implementation. The LED display panel system includes memory management, image format conversion, serial parallel interface (SPI) interface, local scan techniques, LED driver and pulse width modulation (PWM) data control. To reduce I/O ports, data transmission system uses SPI interface to send the PWM data to the LED panels. A novel local scan technique, which could use a lower frequency for data transmission and achieve higher frame rate for LED display, is proposed. Each display module contains local memories for data self-scanning to LED. The display continues even if there is no new data input. The advantages are that the display rate does not care about the speed of data transmission. Only motion area, rather than complete frame, required sending data to display, which can greatly improve data bandwidth. This is very useful for high-resolution display system since even low data rate can achieve the fast display refresh. This approach is a module-based design, which can easily be extended to any size with auto re-configuration without using embedded processor.

关键词： field programmable gate arrays LED displays driver circuits asynchronous circuits data transmission system SPI interface local scan technique display module high-resolution display system high-speed LED display local scanning approach extendable full-colour light LED display panel system memory management pulse width modulation field-programmable gate array asynchronous control asynchronous driver light emitting diode image format conversion LED driver PWM data control I O ports embedded processor

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A review of demodulation techniques for amplitude-modulation atomic force microscopy

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BEILSTEIN JOURNAL OF NANOTECHNOLOGY 2017年第1期8卷 1407-1426页

作者： Ruppert, Michael G. Harcombe, David M. Ragazzon, Michael R. P. Moheimani, S. O. Reza Fleming, Andrew J. Univ Newcastle Sch Elect Engn & Comp Callaghan NSW 2308 Australia Norwegian Univ Sci & Technol NTNU Dept Engn Cybernet Trondheim Norway Univ Texas Dallas Dept Mech Engn Richardson TX 75083 USA

In this review paper, traditional and novel demodulation methods applicable to amplitude-modulation atomic force microscopy are implemented on a widely used digital processing system. As a crucial bandwidth-limiting component in the z-axis feedback loop of an atomic force microscope, the purpose of the demodulator is to obtain estimates of amplitude and phase of the cantilever deflection signal in the presence of sensor noise or additional distinct frequency components. Specifically for modern multifrequency techniques, where higher harmonic and/or higher eigenmode contributions are present in the oscillation signal, the fidelity of the estimates obtained from some demodulation techniques is not guaranteed. To enable a rigorous comparison, the performance metrics tracking bandwidth, implementation complexity and sensitivity to other frequency components are experimentally evaluated for each method. Finally, the significance of an adequate demodulator bandwidth is highlighted during high-speed tapping-mode atomic force microscopy experiments in constant-height mode.

关键词： amplitude estimation atomic force microscopy amplitude modulation digital signal processing field-programmable gate array

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A DBF self-beam steering array antenna for mobile satellite applications using beam-space maximal-ratio combination

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 1999年第3期48卷 665-675页

作者： Miura, R Tanaka, T Horie, A Karasawa, Y MPT Japan Commun Res Lab Yokosuka Radio Commun Res Ctr Kanagawa 2390847 Japan Mitsubishi Elect Co Hyogo Japan Furuno Elect Corp Ltd Hyogo Japan Univ Electrocommun Tokyo Japan

This paper proposes a diversity-receiving array antenna scheme achieved by digital beamforming (DBF) for the purpose of self-beam steering toward the unknown direction-of-arrival (DOA) of a modulated signal in a mobile satellite communications environment, This scheme uses a multibeam former with a spatial fast Fourier transform (FFT) for the received baseband signals to coarsely acquire the attenuated signal, It also uses a self-phasing processor (SPP) applied to the multibeam outputs for precise acquisition and tracking. In the SPP, maximal-ratio combining is achieved with simple digital numerical operations in the complex baseband, allowing for rapidity and stability in beamforming, As a result, the array antenna steers its receiving beam toward the DOA automatically without the need for nonlinear optimization methods. Moreover, the beam is steered toward the DOA of multipath signals according to their signal levels, leading to the optimal cophase recombination of all correlated signals, which improves the quality of the total receiving signal. This paper discusses the scheme, and its performance is evaluated by computational simulation and experiments conducted in a radio anechoic chamber.

关键词： digital beamforming field-programmable gate array maximal ratio combining mobile satellite communication

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Set/Reset Switching Model of Cu Atom Switch Based on Electrolysis

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2017年第4期64卷 1812-1817页

作者： Tada, Munehiro Sakamoto, Toshitsugu NEC Corp Ltd Tsukuba Ibaraki 3058501 Japan

A set/reset switching model of Cu atom switch based on electrolysis is newly proposed. A nanometer-thick solid electrolyte gives a high electric field of similar to 3.3 MV/cm in the solid electrolyte at 2 V, enabling an ionization of Cu and a formation of Cu bridge. It is revealed that the switching voltage depends on the resistance of electrolyte, where the modified Faraday's law of electrolysis with exponential factors on current and time well falls on the experimental on-resistance. The proposed simple compact model is useful for estimating the resistance of the Cu atom switch programmed by any conditions.

关键词： Atom switch conductive-bridging Random access memory field-programmable gate array nonvolatile memory programmable logic device polymer reconfigurable logic solid electrolyte

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An efficient adaptive equalization architecture for high-speed coherent PON systems

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OPTICS COMMUNICATIONS 2020年第0期460卷 125022-000页

作者： Ju, Cheng Liu, Na Li, Changhong Qingdao Univ Coll Elect Informat Qingdao 266071 Peoples R China

Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are imperative to be considered in the transfer of coherent technology from long-haul transmission to passive optical network (PON) application. In this work, a novel low-complexity equalization architecture cascaded two frequency domain equalizers (FDEQs) and one 1-tap 2 x 2 butterfly equalizer is proposed targeting PON applications. FDEQ is designed to handle link chromatic dispersion (CD) and the imperfection of transceiver frequency response. The 1-tap 2 x 2 butterfly equalizer is introduced to realize polarization demultiplexing. A simplified FDEQ tap coefficient calculation method is designed. The performance of the proposed equalization architecture is experimentally verified by a 32-GBaud dual-polarization (DP) Nyquist-QPSK system over 20-km standard single-mode fiber (SSMF) transmission. With the proposed method, the number of hardened multipliers for field-programmable gate array (FPGA) realization is reduced by similar to 90% compared with conventional 2 x 2 butterfly equalizer, at the expense of 0.5 dB receiver sensitivity.

关键词： Coherent receiver Adaptive equalization Low-complexity Passive optical network field-programmable gate array

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Programming paradigms for reconfigurable computing

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MICROPROCESSORS AND MICROSYSTEMS 2005年第10期29卷 435-450页

作者： Lee, G Milne, G Univ Western Australia Sch Comp Sci & Software Engn Perth WA 6009 Australia

High-level programming paradigms are examined to determine their appropriateness for describing systems, which are amenable to automated compilation onto a reconfigurable computing platform. We aim to find a set of language features to act as a basis for future language development which: provide a concise description of the system to be realised;provide clear and intuitive semantics;abstract the underlying technology and are appropriate to the underlying technology. Clearly language design is a subjective process, but we have adopted a systematic approach by assessing the efficacy of existing programming and hardware description languages. We examine the languages Java, VHDL, Standard ML and Circal. Our method also bases the comparison on a set of properties drawn from an archetypal example which we know maps well onto reconfigurable computing platforms. We conclude that none of these established languages has all the properties required for describing reconfigurable computation. This approach leads to insight into the capabilities of existing languages and allows us to determine the essential characteristics of future languages oriented to reconfigurable computing. (C) 2005 Elsevier B.V. All rights reserved.

关键词： circal field-programmable gate array hardware description language Java reconfigurable computing standard ML VHDL

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Asynchronous Cellular Automaton-Based Neuron: Theoretical Analysis and On-FPGA Learning

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IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS 2013年第5期24卷 736-748页

作者： Matsubara, Takashi Torikai, Hiroyuki Osaka Univ Grad Sch Engn Sci Osaka 5608531 Japan

A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

关键词： Asynchronous cellular automaton asynchronous sequential logic bifurcation phenomena field-programmable gate array neuron model nonlinear dynamics on-chip learning

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Integrated synchronous data acquisition subsystem for high-speed GPR system

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IET CIRCUITS DEVICES & SYSTEMS 2019年第7期13卷 1049-1055页

作者： Xu, Xianlei Xia, Tian Ma, Zheng Huston, Dryver China Univ Min & Technol Beijing State Key Lab Coal Resources & Safe Min Beijing 100083 Peoples R China State Key Lab Water Resource Protect & Utilizat C Beijing 100083 Peoples R China Univ Vermont Dept Mech Engn Coll Engn & Math Burlington VT 05405 USA

In this study, an integrated synchronous data acquisition subsystem for high-speed dual-channel ultra-wideband ground penetrating radar (GPR) system is designed and tested. Factors that could cause data missing and asynchronisation are analyzed. According to timing sequence, a field-programmable gate array-based onboard digital control module is integrated to synchronise the data acquisition and data storage subsystems. By applying simultaneous multi-buffer acquisition and readout mode and multi-threading configuration, as well as the critical section control and queue storage structure, the GPR data throughput is considerably improved. For the practicality of this system, a smart End-of-Job control design is performed between different threads to control data acquisition. By using different performance indexes, receiver operation characteristic curve, maximum scan rate, and the rebar detection experiment demonstrate the superiority of author's method.

关键词： data acquisition ground penetrating radar ultra wideband radar field programmable gate arrays integrated synchronous data acquisition subsystem high-speed GPR system data storage subsystems readout mode GPR data throughput field-programmable gate array smart end-of-job control design ground penetrating radar system high-speed dual-channel ultra-wideband radar system timing sequence onboard digital control module multithreading configuration critical section control queue storage structure receiver operation characteristic curve maximum scan rate rebar detection

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FPGA-based hardware-in-the-loop real-time simulation implementation for high-speed train electrical traction system

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IET ELECTRIC POWER APPLICATIONS 2020年第5期14卷 850-858页

作者： Guo, Xizheng Tang, Yiguo Wu, Mingkang Zhang, Ziyu Yuan, Jiaqi Beijing Jiaotong Univ Sch Elect Engn Beijing 100044 Peoples R China China Southern Power Grid Elect Power Res Inst Guangzhou 510663 Peoples R China

The hardware-in-the-loop (HIL) real-time simulation for high-speed train electrical traction system aims to reduce the design cost and speed up control verification process of algorithms in the developmental stage of the traction control unit. In this study, based on the dSPACE real-time simulator, the multiple-simulator, multiple-simulation step of HIL real-time simulation system is first built. Second, for the associated discrete circuit modelling method, an optimisation method is proposed to minimise the switching loss and improve the simulation accuracy by selecting the optimal discrete-time switch admittance parameter, G(S). To decrease the computational burden for field-programmable gate array (FPGA), a decoupling method without simulation latency is presented to reduce the matrix dimension of the system model. Finally, the real-time simulation models of electrical traction system are realised by CPU + FPGA-based simulator, in which the power electronics converter models are computed in FPGA with a fixed 100 ns time-step. The validity and reliability of the real-time simulation system is verified by the HIL simulation and experimental results, which indicate that the real-time HIL simulation at the nanosecond level improves the accuracy essentially.

关键词： traction field programmable gate arrays power convertors railway electrification hardware-in-the loop simulation circuit optimisation matrix algebra microprocessor chips circuit simulation reliability high-speed train electrical traction system hardware-in-the-loop real-time simulation traction control unit dSPACE real-time simulator multiple-simulation step HIL real-time simulation system associated discrete circuit modelling method simulation accuracy discrete-time switch admittance parameter system model CPU plus FPGA-based simulator FPGA-based hardware-in-the-loop real-time simulation control verification process design cost reduction optimisation method switching loss minimization field-programmable gate array decoupling method matrix dimension reduction power electronics converter models reliability real-time HIL simulation model time 100 0 ns

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