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Ultra-Low Complex Blind I/Q-Imbalance Compensation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2019年第9期66卷 3517-3530页

作者： Paireder, Thomas Motz, Christian Kanumalli, Ram S. Sadjina, Silvester Huemer, Mario Intel DMCE A-4040 Linz Austria Johannes Kepler Univ Linz Christian Doppler Lab Digitally Assisted RF Trans A-4040 Linz Austria

Direct-conversion transceivers are the predominating architecture in current mobile communication systems. Despite many advantages, this topology suffers from unavoidable mismatches in the analog part, which causes imbalance between the in-phase and quadrature (I/Q) component. In this paper, we present a novel fully digital, blind I/Q imbalance compensation algorithm that features extremely low computational complexity and high compensation performance for a wide range of input signal types. Different to many state-of-the-art compensation schemes, the approach is not based on a gradient descent optimization and does not require any global feedback. This simplifies the implementation at high data rates and reduces the configuration effort to a minimum. For comparison, we examine an existing method of moment-based estimator with similar properties, for which we also provide the detailed insights beyond available literature. For both algorithms, we provide a rigorous mathematical analysis, which is supported by simulations with a focus on various long-term evolution (LTE) signal types. In addition, hardware architectures, including field-programmable gate array (FPGA) verification, are presented for both algorithms.

关键词： Amplitude and phase imbalance image attenuation long-term evolution direct conversion transceiver field-programmable gate array

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A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第7期71卷 3318-3322页

作者： Lee, Jaewon Jang, Seoyoung Choi, Yujin Kim, Donggeon Yonar, Serdar Braendli, Matthias Ruffino, Andrea Morf, Thomas Kossel, Marcel Francese, Pier-Andrea Kim, Gain Daegu Gyeongbuk Inst Sci & Technol Dept Elect Engn & Comp Sci Daegu 42988 South Korea IBM Res Hybrid Cloud Res Europe Zurich Lab CH-8803 Ruschlikon Switzerland

This brief presents an RFSoC-based functional verification platform for a 2-lane pulse amplitude modulation (PAM) transceiver (TRX) datapath supporting 4-level PAM (PAM-4) and 8-level PAM (PAM-8). Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) existing on the ZU28DR RFSoC are used as digital front-ends of the transmitter (TX) and the receiver (RX), respectively. All digital equalization circuits and adaptation engines required for the modern > 112Gb/s DAC/ADC-DSP-based TRX datapath (excluding clock recovery) are implemented on the programmable logic (PL) running at 50 MHz, enabling real-time functional verification of the DAC/ADC-DSP-based serializer-deserializer (SerDes) operation. The register-transfer-level (RTL) design of the DSP can be directly used for the TRX silicon tape-out once the design is verified with the proposed RFSoC-based platform. The proposed system demonstrates a complete real-time functional verification of the TRX datapath, including the bit-error-rate (BER) test with the BER lower than 10(-9) at 6.4Gb/s and 9.6Gb/s for PAM-4/8 symbols, respectively, with a channel loss of 18 dB at 1.6 GHz.

关键词： Clocks field programmable gate arrays Transceivers Protocols Decision feedback equalizers Connectors Table lookup Serial link DAC/ADC-based serial link wireline transceiver pulse amplitude modulation PAM equalization field-programmable gate array FPGA RFSoC

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A Solid Past, A Vital Future

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IEEE MICRO 2011年第1期31卷 4-5页

作者： Altman, Erik R. ealtman@***

The new Editor in Chief of IEEE Micro introduces himself and the first issue of 2011. He thanks the outgoing Editor in Chief, David Albonesi, for his outstanding work during his tenure. He discusses developments to the magazine and future issues, and asks readers for their suggestions on topics the magazine should cover in coming issues. [ABSTRACT FROM PUBLISHER]

关键词： accelerators big chips Editor in Chief editorial calendar field-programmable gate array FPGA GPU graphics processing unit large systems

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Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2018年第8期26卷 1575-1579页

作者： Liu, Qiang Liu, Jia Sang, Ruoyu Li, Jiajun Zhang, Tao Zhang, Qijun Tianjin Univ Sch Microelect Tianjin 300072 Peoples R China Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China

In this brief, a customized and pipelined hardware implementation of the quasi-Newton (QN) method on field-programmable gate array (FPGA) is proposed for fast artificial neural networks onsite training, targeting at the embedded applications. The architecture is scalable to cope with different neural network sizes while it supports batch-mode training. Experimental results demonstrate the superior performance and power efficiency of the proposed implementation over CPU, graphics processing unit, and FPGA QN implementations.

关键词： Custom computing field-programmable gate array neural network training quasi-Newton (QN) method

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Using FPGA devices to accelerate biomolecular simulations

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COMPUTER 2007年第3期40卷 66-+页

作者： Alam, Sadaf R. Agarwal, Pratul K. Smith, Melissa C. Vetter, Jeffrey S. Caliga, David Oak Ridge Natl Lab Comp Sci & Math Div Future Technol Grp Oak Ridge TN 37831 USA Oak Ridge Natl Lab Computat Biol Inst Oak Ridge TN 37831 USA Oak Ridge Natl Lab Engn Sci & Technol Div Oak Ridge TN 37831 USA

A field-programmable gate array implementation of a molecular dynamics simulation method reduces the microprocessor time-to-solution by a factor of three while using only high-level languages. The application speedup on FPGA devices increases with the problem size. The authors use a performance model to analyze the potential of simulating large-scale biological systems faster than many cluster-based supercomputing platforms.

关键词： biology computing field programmable gate arrays high level languages microprocessor chips molecular biophysics FPGA device biomolecular simulation cluster-basedsupercomputing platform field-programmable gate array high-level language large-scale biolog

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Data Acquisition and Processing Module with a Network Interface for MWPC Detectors with Delay-Line Readout

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JOURNAL OF SURFACE INVESTIGATION 2022年第6期16卷 1023-1028页

作者： Golubev, M. A. Saveleva, T., V Gapon, O. N. Kolkhidashvili, M. R. Polyushkin, A. O. Solovei, V. A. Natl Res Ctr Kurchatov Inst Konstantinov Petersburg Nucl Phys Inst Gatchina 188300 Russia

A prototype of a data acquisition and processing module with a network interface for two-dimensional multiwire proportional chamber detectors with delay-line readout is developed and tested. The device consists of a domestically produced printed circuit board with inputs including a neutron-beam chopper, a neutron-beam monitor and a spin flipper. The board contains a four-channel time-to-code converter, which digitizes the delays between pulses, and a single-board computer with a processor combined with a programmable logic integrated circuit. For this single-board computer, original software is developed that collects and transmits the raw data of the experiment in digital form (coordinates, neutron time-of-flight count, etc.) though the network to the client, and the user interface of the future detector. For data collection, the web server and web client used the firmware language, Verilog programmable logic integrated circuit, programming languages C and JavaScript, respectively. In the future, the tested scheme, implemented in a more compact form, will become an integral part of neutron detectors along with a multi-wire proportional chamber with two-coordinate delay lines and a five-channel analog-signal processing unit. Work with the module, and with the neutron detector in the future, is carried out through a local network in a web browser or an alternative client. The web client for a web browser enables the accumulation of statistics and the viewing of a 2D image from the detector during the experiment, it is also possible to navigate through 2D images of individual time channels for time-of-flight experiments and save all data in the common CSV text format, viewable in office spreadsheets.

关键词： multi-wire proportional chamber delay line field-programmable gate array neutron detector differential non-linearity web interface local area network data processing software hardware data transfer

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Hot Chips 27 Highlights

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IEEE MICRO 2016年第2期36卷 64-69页

作者： Amirtharajah, Rajeevan Robatmili, Behnam Univ Calif Davis Elect & Comp Engn Dept Davis CA 95616 USA

This column discusses some of the designs and presentations from the 2015 Hot Chips Symposium. [ABSTRACT FROM AUTHOR]

关键词： 5G cloud computing datacenter deep learning field-programmable gate array global cache coherency graphics high-performance computing Hot Chips Internet of Things Moore's law multimedia silicon SoC social media Sparc system on chip wireless

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Dual-Hysteresis Band Control of Nine-Switch Inverter to Control Two Induction Motors

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IEEE TRANSACTIONS ON ENERGY CONVERSION 2022年第2期37卷 788-799页

作者： Gulbudak, Ozan Gokdag, Mustafa Karabuk Univ Elect Elect Engn TR-78050 Karabuk Turkey

This paper presents a dual-hysteresis band control method for multi-drive systems based on a nine-switch inverter. The drive system contains two independent three-phase induction motors fed by a nine-switch inverter. Independent control of torque, speed, and stator current of two load stages is achieved. The proposed strategy offers a reliable control operation of both induction machines under individual load profiles. Instead of using independent sets of three-phase voltage source converters, the nine-switch inverter is used to drive separate machines. Thus, the volume and size of the power stage are noticeably reduced due to the use of fewer semiconductors. The theoretical concept and design steps of the proposed method are presented. The performance of the closed-loop independent motor control scheme is experimentally validated using a 3.2 kW lab-scaled nine-switch inverter prototype and Altera Cyclone IV field-programmable gate array.

关键词： Inverters Switches Induction motors Control systems Voltage control Rotors Torque Nine-switch inverter multi-drive systems multi-machines control hysteresis current control variable-speed drives field-programmable gate array

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A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs

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IEEE ACCESS 2020年 8卷 107229-107243页

作者： Vestias, Mario P. Duarte, Rui P. De Sousa, Jose T. Neto, Horacio C. Inst Politecn Lisboa Inst Super Engn Lisboa INESC ID P-1959007 Lisbon Portugal Univ Lisbon Inst Super Tecn INESC ID P-1049001 Lisbon Portugal

Convolutional neural networks have become the state of the art of machine learning for a vast set of applications, especially for image classification and object detection. There are several advantages to running inference on these models at the edge, including real-time performance and data privacy. The high computing and memory requirements of convolutional neural networks have been major obstacles to the broader deployment of CNNs on edge devices. Data quantization is an optimization method that reduces the number of bits used to represent weights and activations of a network model, minimizing storage requirements and computing complexity. Quantization can be applied at the layer level, by using different bit widths in different layers: this is called hybrid quantization. This article proposes a new efficient and configurable architecture for running CNNs with hybrid quantization in low-density field-programmable gate arrays (FPGAs) targeting edge devices. The architecture has been implemented on the Xilinx ZYNQ7020/45 devices and is running the AlexNet and VGG16 networks. Running AlexNet, the architecture has a throughput up to 508 images per second on the ZYNQ7020 device, and 1639 images per second on the ZYNQ7045 device. Considering VGG16, the architecture delivers up to 43 images per second on the ZYNQ7020 device, and 81 images per second on the ZYNQ7045 device. The proposed hybrid architecture achieves up to 13.7 x improvement in performance compared to state-of-the-art solutions, with small accuracy degradation.

关键词： Convolutional neural network deep learning embedded computing field-programmable gate array hybrid quantization

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ASAver.1: An FPGA-based education board for computer architecture system design

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1997年第10期E80A卷 1826-1833页

作者： Ochi, H Kamidoi, Y Kawabata, H Faculty of Information Sciences Hiroshima City University Hiroshima-shi 731-31 Japan

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a pipelined RISC processor within Limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model;it has separate buses for instruction and data memory (''Harvard architecture'') to avoid structural hazard, while it completely ignores data and control hazards to make implementation easy. Although it is such a ''defective'' processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally, every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ri SA rer. I which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor ''ASAP-0'' has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions. From feasibility study result, it is shown that ASAP-0 is described by just 310 lines of Verilog-HDL, and it is implemented to an FPGA device XC5215 with about 1.5-hour runtime of CAD tools. ASAP-0 is so compact that even it can be implemented within a so-called 6,000-gateclass FPGA device XC5206. The proposed education approach has been applied to our department in the last semester, and all of 53 students have completed the experiments successfully.

关键词： education of computer architecture system design DLX-like pipelined RISC processor field-programmable gate array verilog-HDL

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