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FPGA Implementation of Power-Lite Volterra- Inspired Neural Network Equalizer in 100G PON

JOURNAL OF LIGHTWAVE TECHNOLOGY 2024年第9期42卷 3134-3141页

作者： Jiang, Wenqing Huang, Luyao Xu, Yongxin Hu, Weisheng Yi, Lilin Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn State Key Lab Adv Opt Commun Syst & Networks Shanghai 200240 Peoples R China

Electronic nonlinear equalization is a promising technology to compensate for signal impairments in passive optical networks (PONs). However, the high complexity of nonlinear equalizers limits the deployment in application-specific integrated circuits (ASICs). To overcome this problem, we have proposed a Volterra-inspired neural network (VINN) equalizer. It maintains low complexity while providing powerful nonlinear fitting ability. In this paper, weight pruning and quantization are applied for deep joint compression to further decrease the complexity of VINN. The simplified architecture is adapted to field-programmable gate array (FPGA) implementation and enables more than 90% resource conservation. With the aid of a FPGA, VINN is implemented in a single-wavelength 100-Gbps band-limited intensity modulation and direct detection (IMDD) PON system. The efficiency of the proposed real-time VINN equalizer is verified in the experiment. Finally, a 30.34-dB power budget is obtained with the 10-GHz-class transmitter under the bit error ratio (BER) threshold of 1e(-2). Taking into account the diplexer loss, our system is capable to support a power budget over 29 dB in actual applications.

关键词： Deep joint compression field-programmable gate array passive optical network quantization volterra-inspired neural network weight pruning

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Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2021年第4期14卷 1-39页

作者： Lai, Yi-Hsiang Ustun, Ecenur Xiang, Shaojie Fang, Zhenman Rong, Hongbo Zhang, Zhiru Cornell Univ 320 Rhodes Hall Ithaca NY 14853 USA Simon Fraser Univ 8888 Univ Dr Burnaby BC V5A 1S6 Canada Intel 2200 Mission Coll Blvd Santa Clara CA 95054 USA

FPGA-based accelerators are increasingly popular across a broad range of applications, because they offer massive parallelism, high energy efficiency, and great flexibility for customizations. However, difficulties in programming and integrating FPGAs have hindered theirwidespread adoption. Since the mid 2000s, there has been extensive research and development toward making FPGAs accessible to software-inclined developers, besides hardware specialists. Many programming models and automated synthesis tools, such as high-level synthesis, have been proposed to tackle this grand challenge. In this survey, we describe the progression and future prospects of the ongoing journey in significantly improving the software programmability of FPGAs. We first provide a taxonomy of the essential techniques for building a high-performance FPGA accelerator, which requires customizations of the compute engines, memory hierarchy, and data representations. We then summarize a rich spectrum of work on programming abstractions and optimizing compilers that provide different trade-offs between performance and productivity. Finally, we highlight several additional challenges and opportunities that deserve extra attention by the community to bring FPGA-based computing to the masses.

关键词： field-programmable gate array high-level synthesis hardware acceleration domain-specific language

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Digital Filter Architecture Based on Modified Winograd Method F(2x 2, 5x 5) and Residue Number System

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IEEE ACCESS 2023年 11卷 26807-26819页

作者： Valuev, Georgii Valueva, Maria Babenko, Mikhail Tchernykh, Andrei North Caucasus Fed Univ North Caucasus Ctr Math Res Stavropol 355017 Russia Ivannikov Inst Syst Programming Control Management & Appl Math Moscow 109004 Russia CICESE Res Ctr Comp Sci Dept Ensenada 22800 Mexico

Improving the characteristics of digital signal processing devices is an important task in many practical problems. The paper proposes the architecture of a two-dimensional digital filter with a $5\times 5$ mask, in which calculations are performed according to the Winograd method in the Residue Number System (RNS) with moduli of a special type. Theoretical analysis and hardware field-programmable gate array simulation are presented. The results show that the fragment throughput fr/s (number of fragments per second) of the device is 29.6%- 724.7% higher than state-of-the-art solutions. This is achieved by the combination of the Winograd method, which reduces the number of multiplications, with the RNS arithmetic, which performs addition and multiplication under smaller operands in parallel. However, our experiments showed that the proposed method requires up to 2.54%- 11.01% more Look-Up Tables and 3.58%- 19.83% higher power consumption compared to known analogues.

关键词： Filtering Finite impulse response filters Performance evaluation IIR filters Hardware Filtering algorithms Computer architecture Residue number system winograd method field-programmable gate array digital filter digital signal processing

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Efficient Design and Implementation of Energy Detection-Based Spectrum Sensing

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2019年第11期38卷 5187-5211页

作者： Yadav, Pratik V. Alimohammad, Amirhossein Harris, Fred Universal Elect Inc San Diego CA 92121 USA San Diego State Univ Dept Elect & Comp Engn San Diego CA 92182 USA Univ Calif San Diego Dept Elect & Comp Engn San Diego CA 92103 USA

Cognitive radio allows opportunistic spectrum access by finding and using temporally and spatially unused radio channels to enhance the utilization of scarce radio spectrum. Various spectrum sensing techniques have been proposed to detect the availability of unoccupied radio channels. In this article, we first briefly discuss the merits of various spectrum sensing techniques. We then present an efficient hardware architecture for energy detection-based spectrum sensing. We discuss various design parameters and features, such as transform length, window selection, window overlap, ensemble averaging, and dynamic thresholding for efficient realization of the designed spectrum sensing module. Then, an efficient hardware architecture for an optimal energy detection-based spectral estimator is presented. To reduce the computational complexity, we utilize a polyphase filter structure. For the high-performance implementation of the proposed spectrum sensing architecture, we use cutset retiming, and for the compact realization, we use the time-multiplexing technique to reuse hardware resources. We model our spectrum sensing module in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The synthesizable parameteric model of the energy detection-based spectrum sensing module is developed in Verilog hardware description language. The architecture of the designed spectrum sensing module is implemented on a Xilinx Virtex-7 field-programmable gate array and operates at 327 MHz. The cycle-accurate bit-true hardware simulation results are verified against its fixed-point software simulation results. An ASIC architecture of the designed spectrum sensing module is estimated to occupy 5.65mm(2) and dissipate 9.10 mW from a 1.05-V supply while operating at 200 MHz in a standard 32-nm CMOS technology for a 200 MHz bandwidth.

关键词： Spectrum sensing Cognitive radio field-programmable gate array Application-specific integrated circuit

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Concurrent Dual-Band Digital Predistortion Using 2-D Lookup Tables With Bilinear Interpolation and Extrapolation: Direct Least Squares Coefficient Adaptation

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 2017年第4期65卷 1381-1393页

作者： Molina, Albert Rajamani, Kannan Azadet, Kamran Intel Corp Madrid 28020 Spain Intel Corp Allentown PA 18019 USA Intel Corp Santa Clara CA USA

In this paper, we present a method to implement concurrent dual-band digital predistortion (DPD) models using 2-D lookup tables (LUTs) with bilinear interpolation and extrapolation. We introduce the required set of basis functions to describe this model. The DPD output is expressed as a linear combination of these basis functions and we show how to directly estimate the coefficients using least squares. We introduce a flexible 2-D bilinear extrapolation scheme that is ideally suited to dual-band signals with high peak-to-average power ratio. We show how these are needed when digital predistortion is implemented in conjunction with automatic gain control. We also introduce example dual-band polynomial models with memory and show how to create a similar memory model based on 2-D lookup tables with bilinear interpolation. One such model is the dual-band generalized memory polynomial model. Laboratory experiments are performed using such a 2-D LUT with bilinear interpolation model.

关键词： Automatic gain control (AGC) bilinear extrapolation bilinear interpolation cellular base station digital predistortion (DPD) DPD adaptation dual band field-programmable gate array generalized memory polynomial (GMP) nonlinear distortion power amplifiers (PAs) 2-D lookup table (LUT) vector processor

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Design and Synchronization of Chaos-Based True Random Number Generators and Its FPGA Implementation

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IEEE ACCESS 2022年 10卷 8279-8286页

作者： Liao, T. L. Wan, P. Y. Yan, Jun-Juh Natl Cheng Kung Univ Dept Engn Sci Tainan 701 Taiwan Natl Chin Yi Univ Technol Dept Elect Engn Taichung 41107 Taiwan

In this paper, a new chaos-based true random number generator (TRNG) and a sliding mode controller (SMC) to synchronize the proposed TRNGs are proposed. Firstly, the continuous chaotic system is transformed into a discrete system that preserves the original continuous system's chaotic behavior and makes it easy to realize with the field-programmable gate array (FPGA) for synchronization control. Then, a discrete SMC is introduced to solve the synchronization problem of the master-slave discrete chaotic systems. Subsequently, a novel hybrid function integrated with the El-Gamal algorithm is proposed to complete the TRNG design. Finally, the FPGA-based realization of the synchronized master-slave TRNGs is implemented. The randomness quality of the proposed TRNGs has been ensured by using Shannon's entropy and histogram analysis. Furthermore, the National Institute of Standards and Technology (NIST) test suite has also been introduced to evaluate the proposed TRNGs and compare with the existing results in the literature.

关键词： Synchronization Generators field programmable gate arrays Chaotic communication Main-secondary Heuristic algorithms Signal processing algorithms True random number generators chaotic systems synchronization sliding mode control field-programmable gate array

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System design consideration for digital wheelchair controller

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2000年第4期47卷 898-907页

作者： Chen, RX Chen, LG Chen, LL Natl Taiwan Univ DSPIC Lab Dept Elect Engn Taipei Taiwan

The design and implementation of a digital wheelchair controller system is presented in this paper. This novel model depicts an information flow between the driving commands and wheel speed. A command interpreter and two speed processing datapaths are proposed as functionally independent blocks for the controller. The control process consists of the following steps: command decoding, speed estimation, and speed serving. Through proper partitioning to concurrent blocks, the design complexity is reduced significantly. Block reconfiguration for field-programmable gate array rapid prototyping is also employed in this paper, and system fidelity and development efficiency are revealed through the experimental results.

关键词： block design electrical differential gears field-programmable gate array proportional integral derivative control pulsewidth modulation rapid prototyping rotary encoders speed estimators speed models voice driven wheelchair controllers

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A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2021年第4期17卷 1–15页

作者： Gan, Victor M. Liang, Yibin Li, Lianjun Liu, Lingjia Yi, Yang Virginia Polytech Inst & State Univ 1185 Perry St Blacksburg VA 24061 USA

The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks. The proposed architecture includes a linear combination processor with negligible deployment of configurable logic blocks and a high-accuracy nonlinear function approximator. Our work is verified with the prediction task on the classical NARMA dataset and a symbol detection task for orthogonal frequency division multiplexing systems using a wireless communication testbed built on a software-defined radio platform. Experiments and performance measurement show that the new ESN architecture is capable of processing real-world data efficiently for low-cost and low-power applications.

关键词： Reservoir computing echo state network field-programmable gate array digital signal processing symbol detection OFDM wireless communication

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Offloading Collective Operations to programmable Logic

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IEEE MICRO 2017年第5期37卷 52-60页

作者： Arap, Omer Brasilino, Lucas R. B. Kissel, Ezra Shroyer, Alexander Swany, Martin Indiana Univ Bloomington IN 47405 USA Indiana Univ Intelligent Syst Engn Dept Bloomington IN 47405 USA Indiana Univ Experience Microcontroller Data Acquisit Devices Bloomington IN 47405 USA Indiana Univ Intelligent Syst Engn Dept Sch Informat & Comp Bloomington IN 47405 USA

In this article, the authors present a framework for offloading collective operations to programmable logic for use in applications using the Message Passing Interface (MPI). They evaluate their approach on the Xilinx Zynq system on a chip and the NetFPGA, a network interface card based on a field-programmable gate array. Results are presented from microbenchmarks and a benchmark scientific application.

关键词： Algorithm design and analysis collective operations field programmable gate arrays field-programmable gate array FPGA message passing interface MPI Network interfaces Ports (Computers) Programming Random access memory SoC system on a chip Zynq

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GIVING TEXT ANALYTICS A BOOST

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IEEE MICRO 2014年第4期34卷 6-14页

作者： Polig, Raphael Atasu, Kubilay Chiticariu, Laura Hagleitner, Christoph Hofstee, H. Peter Reiss, Frederick R. Zhu, Huaiyu Sitaridi, Eva IBM Res Zurich Res Lab Zurich Switzerland IBM Res Intelligent Informat Syst Grp Zurich Switzerland IBM Res Accelerator Technol Grp Zurich Switzerland IBM Res Zurich Switzerland Columbia Univ Dept Comp Sci New York NY 10027 USA

TRADITIONAL SERVER ARCHITECTURES CANNOT ANALYZE BIG DATA EFFICIENTLY. BY USING A STREAMING HARDWARE ACCELERATOR IMPLEMENTED IN RECONFIGURABLE LOGIC, THE AUTHORS CAN IMPROVE THE THROUGHPUT OF SYSTEMT'S INFORMATION EXTRACTION QUERIES BY AN ORDER OF MAGNITUDE. SUCH A SYSTEM CAN BE DEPLOYED BY EXTENDING SYSTEMT'S EXISTING COMPILATION FLOW AND USING A MULTITHREADED COMMUNICATION INTERFACE THAT CAN UTILIZE THE ACCELERATOR'S BANDWIDTH.

关键词： Big data Computer architecture field programmable gate arrays field-programmable gate array hardware hardware accelerator heterogeneous system Instruction sets text analytics Text mining Text processing

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