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An efficient design for real-time obstructive sleep apnea OSA detection through esophageal pressure Pes signal

BIOMEDICAL ENGINEERING-BIOMEDIZINISCHE TECHNIK 2021年第5期66卷 473-487页

作者： Ben Salah, Ghada Abbes, Karim Abdelmoula, Chokri Naji, Baligh Masmoudi, Mohamed Abdelmoula, Mohamed Hedi Turki, Mohamed Univ Sfax Natl Sch Engineers Sfax ENIS Elect Engn Dept METS LabENIS St Soukra Sfax 3038 Tunisia Univ Sfax Fac Sci Sfax FSS Phys Dept METS Lab Sfax Tunisia Univ Sfax Natl Sch Elect & Telecommun Sfax ENET Com Ind Comp Dept METS Lab Sfax Tunisia CHU Habib Bourguiba Sfax Maxillo Facial Surg Dept Sfax Tunisia Tunisian Soc Sleep Med TSSM Tunis Tunisia

Obstructive Sleep Apnea (OSA) is a potentially common sleep disorder in which the upper airways are collapsed either partially or completely. The golden standard method for treating OSA, is the full night Continuous Positive Airway Pressure (CPAP). Yet, due to the ensuing discomfort, it incurs on patients, researchers have been motivated to investigate other alternatives, whereby, OSA can be effectively treated. Recently, an increasingly popular OSA treatment has been developed that consists in activating the protrusion muscles of the tongue by stimulating the Hypoglossal Nerve (HGN). In this context, the present work is conducted to propose the design of apnea detector module as part of an implantable HGN stimulator based on the esophageal Pressure Pes signal as a new approach for controlling OSA occurrence. Specifically, an effective real-time apnea event detecting algorithm is put forward. Following the achievement of satisfactory simulation results, attained through the Modelsim simulation tool, we proceeded with assessing the possibility of its hardware implementation on a field-programmable gate array (FPGA) device. To this end, the apnea detector module was synthesized and designed. The low power consumption and the small size, characterizing this module, which have made it possible to integrate it as part of a wirelessly-powered implantable HGN stimulator.

关键词： apnea events field-programmable gate array hardware implementation hypoglossal nerve stimulator negative esophageal pressure obstructed upper airway

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FPGA-based real-time 3D image preprocessing for image-guided medical interventions

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2007年第4期1卷 285-301页

作者： Dandekar, Omkar Castro-Pareja, Carlos Shekhar, Raj Univ Maryland Dept Diagnost Radiol & Nucl Med Baltimore MD 21201 USA Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

Minimally invasive image-guided interventions (IGIs) are time and cost efficient, minimize unintended damage to healthy tissue, and lead to faster patient recovery. One emerging trend in IGI workflow is to use volumetric imaging modalities such as low-dose computed tomography (CT) and 3D ultrasound to provide real-time, accurate anatomical information intraoperatively. These intraoperative images, however, are often characterized by quantum (in low-dose CT) or speckle (in ultrasound) noise and must be enhanced prior to any advanced image processing. Anisotropic diffusion filtering and median filtering have been shown to be effective in enhancing and improving the visual quality of these images. However, achieving real-time performance, as required by IGIs, using software-only implementations is challenging because of the sheer size of the images and the arithmetic complexity of the filtering operations. We present a field-programmable gate array-based reconfigurable architecture for real-time preprocessing of intraoperative 3D images. The proposed architecture provides programmable kernels for 3D anisotropic diffusion filtering and 3D median filtering within the same framework. The implementation of this architecture using an Altera Stratix-II device achieved a voxel processing rate close to 200 MHz, which enables the use of these processing techniques in the IGI workflow prior to advanced operations such as segmentation, registration, and visualization.

关键词： Image-guided interventions 3D anisotropic diffusion 3D median filtering Real-time image processing field-programmable gate array

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Compact Rayleigh and Rician fading simulator based on random walk processes

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IET COMMUNICATIONS 2009年第8期3卷 1333-1342页

作者： Alimohammad, A. Fard, S. F. Cockburn, B. F. Schlegel, C. Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

This article describes a significantly improved sum-of-sinusoids-based model for the accurate simulation of time-correlated Rayleigh and Rician fading channels. The proposed model utilises random walk processes instead of random variables for some of the sinusoid parameters to more accurately reproduce the behaviour of wireless radio propagation. Every fading block generated using our model has accurate statistical properties on its own and hence, unlike previously proposed models, there is no need for time-consuming ensemble-averaging over multiple blocks. Using numerical simulation it is shown that the important statistical properties of the generated fading samples have excellent agreement with the theoretical reference functions. A fixed-point hardware implementation of the corresponding Rayleigh and Rician fading channel simulator on a field-programmable gate array (FPGA) is presented. By efficiently scheduling the operations, the reconfigurable fading channel simulator is compact enough that it can be efficiently used to simulate multipath scenarios and multiple-antenna systems (e. g. a 4 x 4 MIMO channel) using a single FPGA.

关键词： statistical analysis Rician fading channel simulator time-correlated compact Rayleigh channel multipath channels Logic circuits multipath scenario radiowave propagation sinusoid parameter Radiowave propagation field programmable gate arrays field-programmable gate array Rician channels antenna arrays Antenna arrays scheduling random processes statistical property simulation wireless radio propagation multiple antenna system random walk process Radio links and equipment Rayleigh channels Other topics in statistics

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Improved ring oscillator PUF on FPGA and its properties

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MICROPROCESSORS AND MICROSYSTEMS 2016年第PartA期47卷 55-63页

作者： Kodytek, Filip Lorencz, Robert Bucek, Jiri Czech Tech Univ Fac Informat Technol Thakurova 9 Prague Czech Republic

PUFs (Physical Unclonable Function) are increasingly used in proposals of security architectures for device identification and cryptographic key generation. Many PUF designs for FPGAs proposed up to this day are based on ring oscillators (RO). The classical approach is to compare frequencies of ROs and produce a single output bit from each pair of ROs based on the result of comparison of their frequencies. This ROPUF design requires all ROs to be mutually symmetric and also the number of pairs of ROs is limited in order to preserve the independence of bits in the PUF response. This led us to design a new ROPUF on FPGA which is capable of generating multiple output bits from each pair of ROs and is also allowing to create higher number of pairs of ROs, thereby making the use of ROs more efficient than the classical approach. Our PUF design is based on selecting a particular part of a counter value and using it for the PUF output. By applying Gray code on the counter values, we have considerably improved the PUF's statistical properties. In principle, this PUF design does not need the ROs to be mutually symmetric, however, it is shown that this ROPUF design has significantly better properties with varying supply voltage when symmetric ROs are used. All of the presented measurements were performed on Digilent Basys 2 FPGA Boards (Xilinx Spartan3E-100 CP132). In this work, we provide a more detailed description of the PUF design on FPGA and the behaviour of ROs with varying supply voltage. Our proposed PUF architecture offers more output bits with required statistical properties from each RO pair than the classical approach, where frequencies of ROs are compared. The presented improvements significantly reduce the dependence on fluctuation of supply voltage. (C) 2016 Elsevier B.V. All rights reserved.

关键词： Physical unclonable function field-programmable gate array Ring oscillator

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A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2015年第2期31卷 207-215页

作者： Pereira, Igor Gadelha Dias, Leonardo Alves de Souza, Cleonilson Protasio Fed Univ Paraiba UFPB Dept Elect Engn Joao Pessoa Paraiba Brazil

This paper describes the implementation of a shift-register based Built-In Self-Test (BIST) architecture for FPGA global interconnection resources testing. Through this, it is possible to configure FPGA resources that need to be tested in order to obtain high reliability FPGA-based systems. The proposed BIST approach takes advantage of FPGA low-level resources in order to generate cyclic test patterns, analyse testing response and store test results in a simple way. Additionally, the same BIST configuration set is capable of diagnosing the tested interconnection resources with no additional configurations thereby reducing time requirements. This paper presents the proposed BIST architecture and its diagnosis scheme, its implementation on a Xilinx FPGA, and experimental results.

关键词： Built-in self-test field-programmable gate array Global interconnection resource testing FPGA testing and diagnosis

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Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices

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MICROELECTRONICS JOURNAL 2019年第Jan.期83卷 39-49页

作者： Suzuki, Daisuke Oka, Takahiro Hanyu, Takahiro Tohoku Univ Frontier Res Inst Interdisciplinary Sci Sendai Miyagi 9808578 Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi 9808577 Japan

A circuit optimization technique of nonvolatile logic-in-memory (NVLIM)-based lookup table (LUT) circuits in conjunction with magnetic-tunnel junction (MTJ) devices is proposed. Three important points should be considered for the circuit optimization technique of the NVLIM-based LUT circuit. One is optimizing DC and transient characteristics of the read current path, another is minimizing the effect of capacitance of both read-access transistors and write-access transistors, the other is how to design the selector circuit. As a typical example, the NVLIM-based LUT circuits is designed using 55 nm CMOS technology with two types of MTJ devices;the output delay, power and area of the circuit are evaluated. As a result, the output delay in the NVLIM-based 6-input LUT circuit is reduced by 47% compared to that of conventional SRAM-based implementation with 27% lower active power consumption as well as 67% of area reduction.

关键词： Magnetic tunnel junction device field-programmable gate array Lookup-table circuit Circuit optimization

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Efficient parallel implementation of reservoir computing systems

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NEURAL COMPUTING & APPLICATIONS 2020年第7期32卷 2299-2313页

作者： Alomar, M. L. Skibinsky-Gitlin, Erik S. Frasser, Christiam F. Canals, Vincent Isern, Eugeni Roca, Miquel Rossello, Josep L. Univ Balearic Isl Dept Phys Elect Engn Grp Ctra Valldemossa Km 7-5 Palma De Mallorca 07122 Spain

Reservoir computing (RC) is a powerful machine learning methodology well suited for time-series processing. The hardware implementation of RC systems (HRC) may extend the utility of this neural approach to solve real-life problems for which software solutions are not satisfactory. Nevertheless, the implementation of massive parallel-connected reservoir networks is costly in terms of circuit area and power, mainly due to the requirement of implementing synapse multipliers that increase gate count to prohibitive values. Most HRC systems present in the literature solve this area problem by sequencializing the processes, thus loosing the expected fault-tolerance and low latency of fully parallel-connected HRCs. Therefore, the development of new methodologies to implement fully parallel HRC systems is of high interest to many computational intelligence applications requiring quick responses. In this article, we propose a compact hardware implementation for Echo-State Networks (an specific type of reservoir) that reduces the area cost by simplifying the synapses and using linear piece-wise activation functions for neurons. The proposed design is synthesized in a field-programmable gate array and evaluated for different time-series prediction tasks. Without compromising the overall accuracy, the proposed approach achieves a significant saving in terms of power and hardware when compared with recently published implementations. This technique pave the way for the low-power implementation of fully parallel reservoir networks containing thousands of neurons in a single integrated circuit.

关键词： Artificial neural networks Recurrent neural networks Reservoir computing Echo sate networks Hardware neural network field-programmable gate array Time-series prediction

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FPGA-based implementation of different families of fractional-order chaotic oscillators applying Grunwald-Letnikov method

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COMMUNICATIONS IN NONLINEAR SCIENCE AND NUMERICAL SIMULATION 2019年第Jun.期72卷 516-527页

作者： Dalia Pano-Azucena, Ana Ovilla-Martinez, Brisbane Tlelo-Cuautle, Esteban Manuel Munoz-Pacheco, Jesus Gerardo de la Fraga, Luis INAOE Dept Elect Puebla 72840 Mexico Univ Autonoma Metropolitana Unidad Iztapalapa Mexico City 09340 DF Mexico BUAP Fac Elect Sci Puebla 72570 Mexico CINVESTAV Comp Sci Dept Mexico City 07360 DF Mexico

Fractional-order chaotic oscillators are a hot topic of research and nowadays many new mathematical models have been introduced, which can be suitable for the development of novel applications in all related fields of science and engineering. However, the challenge is their implementation that can be performed using electronic devices. In this manner, we highlight the implementation of different families of fractional-order chaotic oscillators using field-programmable gate arrays (FPGAs). We detail the hardware implementation when solving the mathematical models applying the Grunwald-Letnikov method, and highlight the short-memory principle, which memory length is designed using specialized random-access-memory and read-only-memory blocks. In addition, we show how to reduce hardware resources by reusing blocks that are controlled by an especial architecture that is introduced herein, in order to perform an efficient processing of the data. Finally, using Cyclone IV GX FPGA DE2i-150 from Altera, DAS1612 digital-to-analog converter and fixed-point arithmetic of 32 bits, we provide experimental results that were observed in a Lecroy's oscilloscope showing working frequencies of fractional-order chaotic attractors between 77.59 and 84.9 MHz. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Fractional-order chaotic oscillator field-programmable gate array Grunwald-Letnikov method Fixed-point arithmetic

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Homogeneous charge compression ignition combustion stability improvement using a rapid ignition system

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INTERNATIONAL JOURNAL OF ENGINE RESEARCH 2020年第10期21卷 1846-1856页

作者： Gordon, David Wouters, Christian Kinoshita, Shota Wick, Maximilian Lehrheuer, Bastian Andert, Jakob Pischinger, Stefan Koch, Charles R. Univ Alberta Dept Mech Engn 116 St & 85 Ave Edmonton AB T6G 2R3 Canada Rhein Westfal TH Aachen Inst Combust Engines Aachen Germany SOKEN INC Res Div 1 Res Dept 12 Tokyo Japan FEV Europe GmbH Aachen Germany Rhein Westfal TH Aachen Mechatron Syst Combust Engines Aachen Germany

When compared to traditional engines, homogeneous charge compression ignition has the potential to significantly reduce NOx raw emissions, while maintaining a high fuel efficiency. Homogeneous charge compression ignition is characterized by compression-induced autoignition of a lean homogeneous air-fuel mixture. Since homogeneous charge compression ignition does not utilize direct ignition control, it is strongly dependent on the state of the cylinder charge and can suffer from high cyclic variability. With spark-assisted compression ignition, it has been demonstrated that misfires can be reduced, while preserving the high thermal efficiency of homogeneous charge compression ignition as a result of the more favorable physical mixture properties due to dilution. However, spark-assisted compression ignition reduces the NOx benefits of homogeneous charge compression ignition, as it increases the local combustion temperatures. To merge the advantages of the homogeneous charge compression ignition and the spark-assisted compression ignition combustion processes, a field-programmable gate array for detailed simulation of the physical gas exchange is combined with a rapid spark system. The low latency and computational speed of the field-programmable gate array allows the simulation process to be implemented in real time. When combined with the rapid reaction time of the high-frequency current-based rapid ignition system, a feedforward controller based on the cylinder pressure or heat release is realized. The developed model-based controller determines if a spark is required to assist the homogeneous charge compression ignition combustion process. The use of the field-programmable gate array and rapid ignition system allows for the calculation of combustion properties and controller output within 0.1 similar to CA. This article presents the development and experimental validation of the developed controller on a single-cylinder research engine. The combustion stability has

关键词： field-programmable gate array homogeneous charge compression ignition gasoline-controlled autoignition gas exchange model zero-dimensional engine simulation model-based control rapid ignition system spark-assisted compression ignition

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A Modified Algorithm for the L/C-based Switch Model of Power Converters in Real-Time Simulation Based on FPGA

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS 2024年第5期60卷 7030-7037页

作者： Wang, Can Wang, Qinsheng Weng, Haowen Pan, Xuewei Harbin Inst Technol Shenzhen 518055 Peoples R China

In order to solve the problem of virtual power loss introduced by the L/C-based switch model in real-time simulation of power electronic converters, a modified algorithm is proposed which can be adopted in the L/C-based switch model. This paper analyzes the causes of virtual power loss from a numerical algorithm perspective and concludes that the primary cause is the initial error of the L/C-based switch model during switching. Therefore, an additional modified algorithm is proposed to eliminate it. To minimize the impact of the proposed algorithm on the computation speed and resource consumption of field-programmable gate array (FPGA) in real-time simulation, an FPGA implementation architecture is proposed. Compared with the conventional electromagnetic transient simulation algorithm, the proposed algorithm only requires one additional clock cycle and barely increases the resource consumption. The effectiveness and superiority of the proposed algorithm are verified on a self-built FPGA-based real-time simulation platform.

关键词： L/C-based switch model real-time simulation field-programmable gate array virtual power loss L/C-based switch model real-time simulation field-programmable gate array virtual power loss

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