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DRAF: A LOW-POWER DRAM-BASED RECONFIGURABLE ACCELERATION FABRIC

IEEE MICRO 2017年第3期37卷 70-78页

作者： Gao, Mingyu Delimitrou, Christina Niu, Dimin Malladi, Krishna T. Zheng, Hongzhong Brennan, Bob Kozyrakis, Christos Stanford Univ Dept Elect Engn Stanford CA 94305 USA Cornell Univ Dept Elect & Comp Engn Ithaca NY 14853 USA Cornell Univ Dept Comp Sci Ithaca NY 14853 USA Samsung Semicond US R&D Ctr Memory Solut Lab San Jose CA USA Stanford Univ Dept Comp Sci Stanford CA 94305 USA

The DRAM-Based Reconfigurable Acceleration Fabric (DRAF) uses commodity DRAM technology to implement a bit-level, reconfigurable fabric that improves area density by 10 times and power consumption by more than 3 times over conventional field-programmable gate arrays. Latency overlapping and multicontext support allow DRAF to meet the performance and density requirements of demanding applications in datacenter and mobile environments.

关键词： DRAM field-programmable gate array FPGA low power reconfigurable logic

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High-Speed Real-Time Simulation for Power Electronic Systems

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SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL 2008年第8-9期84卷 441-456页

作者： Word, Dale Bednar, Richard Zenor, John J. Hingorani, Nari G. Calif State Univ Chico Dept Elect & Comp Engn Chico CA 95929 USA Calif State Univ Chico McLeod Inst Simulat Sci Chico CA 95929 USA Independent Consultant Los Altos Hills CA 94022 USA

Real-time simulators have been used as an aid to power system design for many years. Over time, scaled-down physical models and analog computer-based simulators have given way to real-time simulators based on digital technology. Another trend has been the need for shorter and shorter frame times for these digital real-time simulators. Modern power electronic systems use high-frequency Pulse-Width Modulated (PWM) controllers. Indications are that frame times of 2 mu S are needed for PWM switching frequencies of 10 KHz. As frequencies increase further it is possible that frame times of less than 1 mu S may be required. In order to achieve these very short frame times, the implementation of this type of simulator requires careful selection of the methods and technologies used. The first involves thorough analysis of the integration method chosen, to ensure that it provides the performance, stability and accuracy required. Additionally, the choice of computing platform is crucial to provide the computational support to meet these very aggressive timing requirements.

关键词： simulation power electronics real-time Digital Signal Processors field-programmable gate array

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Electrical and optical clock and data recovery in optical access networks: a comparative study

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INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS 2016年第17期29卷 2555-2564页

作者： Abd El-Khaleq, Esraa El-Sayed, Yasmine Ismail, Tawfik Mostafa, Hassan Cairo Univ Dept Elect & Commun Fac Engn Giza Egypt Cairo Univ Natl Inst Laser Enhanced Sci Dept Engn Applicat Laser Giza Egypt

Clock and data recovery (CDR) is an essential part in high-speed telecommunication systems. The CDR is used to extract the clock and re-time the received data, which allows a synchronous operation to recover the transmitted signal. In optical access networks, electrical CDR or optical CDR implementations can be used. However, there are no clear guidelines or recommendations on which CDR implementation should be adopted for better performance. These missing clear recommendations are because the electrical CDR requires electronics design expertise whereas the optical CDR requires optical design expertise. Consequently, in this paper, an all-digital CDR, designed and implemented on the field-programmable gate array platform, and an optical CDR, developed by using fiber Bragg grating technology on the OptiSystem platform, are presented. Furthermore, the integration of these 2 CDR implementations with the optical access network is implemented, and their performance is evaluated for various transmission rates and communication distances. Finally, a comparative study in terms of the bit error rate between the all-digital CDR and the optical CDR is presented.

关键词： clock and data recovery fiber Bragg grating field-programmable gate array optical access network

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A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems

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APPLIED SOFT COMPUTING 2007年第3期7卷 979-994页

作者： Salcic, Zoran Coghill, George Maunder, Bruce Univ Auckland Dept Elect & Comp Engn Auckland New Zealand

In this paper we present a methodology for optimizing complex datapath oriented digital circuits. An optimizer was developed based on the earlier development of an automatic circuit synthesizer that synthesizes hardware description language specifications based on available functional modules. A genetic algorithm is tailored to the problem of digital circuit optimization through the development of specific structures and procedures. In particular, a concise encoding of the circuit is developed that the genetic algorithm can manipulate. Specific crossover and mutation mechanisms are also developed to complement the functionality of the synthesizer. The searches are effected by altering module data type, hardware resource sharing, and module implementation version. A fitness function is derived that makes use of a number of optimization parameters to objectively evaluate each particular circuit. The features of each circuit are calculated and estimated during the analysis phase. (c) 2006 Elsevier B. V. All rights reserved.

关键词： optimization data-flow genetic algorithm high-level synthesis field-programmable gate array

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LED dimming with efficiency considered

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ELECTRONICS LETTERS 2011年第7期47卷 457-458页

作者： Hwu, K. I. Tu, W. C. Natl Taipei Univ Technol Dept Elect Engn Taipei 10608 Taiwan

A LED dimming circuit, together with the KY converter, is presented, which is controlled based on a field-programmable gate array. Via the proposed feedback control strategy, the voltage across the linear current regulator is reduced so as to upgrade the efficiency of the overall system, with the proposed maximum error selection based on a suitable voltage turning on the diode. Aside from this, each LED string takes direct dimming, and is powered by the KY converter, which has an output inductor and hence upgrades the life of the output capacitor. Experimental results show that the efficiency based on the proposed control method is higher than that based on the traditional control one, particularly at light load.

关键词： LED dimming field programmable gate arrays field-programmable gate array light emitting diodes linear current regulator voltage regulators voltage turning

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20-Bit RISC and DSP System Design in an FPGA

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COMPUTING IN SCIENCE & ENGINEERING 2014年第2期16卷 16-20页

作者： Tomar, Amit Kumar Singh Jain, Rita Lakshmi Narain College of Technology India

Today, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer core with several operations performed by a digital signal processor system. Here, the design of a RISC and DSP system is presented that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.

关键词： ALU CPU CU FPGA GPR IR MACs PC RISC RS VLIW arithmetic logic unit control unit field-programmable gate array general-purpose register instruction register multiply and accumulates program counter reduced instruction set computer register set scientific computing very large instruction word

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FPGA implementation of AES encryptor based on rolled and masked approach

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INTERNATIONAL JOURNAL OF INFORMATION AND COMPUTER SECURITY 2023年第1-2期21卷 1-18页

作者： Mathur, Monika Goel, Nidhi IGDTUW Dept ECE Kashmere Gate Delhi India

The present work proposes a modified 8-bit AES architecture that performs AES core operations in a single round wherein data is iterated ten times instead of having ten different rounds leading to substantial decrease in area and power consumption. To enhance the security of AES encryption, boolean masking has been employed for all AES operations, rounds and intermediate data. Modified architecture for AddRoundKey and ByteSubstitution operation has been proposed that employs high order masking. Also, an enhanced key expansion algorithm is proposed that makes AES less vulnerable to saturation attacks and differential power analysis (DPA) attacks. Implementation of the proposed architecture has been done using Vivado Design Suite on Virtex-7 FPGA. Result analysis depicts that, during the performance explore strategy, 179.73 MHz maximum frequency with a throughput of 143.78 Mbps has been achieved whereas, the proposed architecture utilises 757 slices, 962 LUTs and 0.313 watt power using area explore strategy.

关键词： advanced encryption standard AES field-programmable gate array FPGA Boolean masking enhanced key expansion algorithm DPA attack rolled architecture

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A hardware/software architecture dedicated to model predictive control law and implemented into an FPGA platform

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INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL 2019年第3期13卷 301-323页

作者： Sirine, Telmoudi Brini Badreddine, Bouzouita Faouzi, Bouani Turns El Manar Univ Natl Engn Sch Tunis ENIT LR11ES20 Lab Anal Concept & Control Syst Tunis Tunisia Univ Sousse Natl Engn Sch Sousse Sousse Tunisia

Model predictive control (MPC) is an optimisation-based strategy for high-performance control engineering practice and real-time applications. This method needs to solve online a quadratic programming (QP) problem at each sample time to find optimal control sequence. In this paper, a new optimised MPC architecture is presented, for a gradient-based QP solver to implement linear MPC on a field-programmable gate array platform, which allows obtaining high-quality performances for the real-time control applications. It requires a manual programming of the high-level C/C ++ code in opposition to the other presented approaches, which automatically generates the code. The efficiency of this approach is completed with real time control of the water level of a single tank system running on a Nanoboard 3000XN chip using a conception environment (Altium Designer), while comparing between the MPC and PID controllers.

关键词： field-programmable gate array FPGA predictive control quadratic optimisation problem PID controller Altium designer model predictive control MPC

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Towards deterministic FPGA reconfiguration

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2020年第2期13卷 236-253页

作者： Reis, Joao Gabriel Frohlich, Antonio Augusto Univ Fed Santa Catarina Software Hardware Integrat Lab BR-88040900 Florianopolis SC Brazil

Rigid partitioning of components in hardware/software co-design flows can lead to suboptimal choices in embedded systems with dynamic runtime requirements. FPGAs allow systems to cope with such unforeseen conditions by changing portions of hardware dynamically while other parts are still active. Nevertheless, to guarantee a transparent reconfiguration, it is necessary to ensure that it does not disrupt the timing requirements of the running tasks and vice-versa. This work proposes a deterministic FPGA reconfiguration mechanism capable of mitigating the interference generated by I/O operations occurring in parallel. The reconfiguration is confined in the idle time without interfering with or being interfered by other activities occurring in the system, including peripherals performing I/O. The scheme decomposes the reconfiguration process in small steps such that it is preemptable, and compliant with timing requirements. To quantify the impact of I/O interference on FPGA reconfiguration, we measured the execution time to load bitstreams from memory to the FPGA reconfiguration interface with multiple peripherals performing I/O in parallel. Results show that if the I/O interference is not taken into account and mitigated, the reconfiguration time can grow up to 8,800% when peripherals are performing I/O operations through DMA.

关键词： field-programmable gate array FPGA dynamic reconfiguration I/O interference embedded systems partial reconfiguration power management interference mitigation speculative reconfiguration operating system

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FPGA implementation of population-based ant colony optimization

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APPLIED SOFT COMPUTING 2004年第3期4卷 303-322页

作者： Scheuermann, B So, K Guntsch, M Middendorf, M Diessel, O ElGindy, H Schmeck, H Univ Karlsruhe TH Inst AIFB Karlsruhe Germany Univ New S Wales Kensington NSW 2033 Australia Univ Leipzig Inst Comp Sci Leipzig Germany

We present a hardware implementation of population-based ant colony optimization (P-ACO) on field-programmable gate arrays (FPGAs). The ant colony optimization meta-heuristic is adopted from the natural foraging behavior of real ants and has been used to find good solutions to a wide spectrum of combinatorial optimization problems. We describe the P-ACO algorithm and present a circuit architecture that facilitates efficient FPGA implementations. The proposed design shows modest space requirements but leads to a significant reduction in runtime over software-based solutions. Several modifications and extensions of the basic algorithm are also presented, including the approximation of the heuristic function by a small, dynamically changing set of favorable decisions. (C) 2004 Elsevier B.V. All rights reserved.

关键词： ant colony optimization ant algorithm field-programmable gate array FPGA

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