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FPGA implementation of population-based ant colony optimization

APPLIED SOFT COMPUTING 2004年第3期4卷 303-322页

作者： Scheuermann, B So, K Guntsch, M Middendorf, M Diessel, O ElGindy, H Schmeck, H Univ Karlsruhe TH Inst AIFB Karlsruhe Germany Univ New S Wales Kensington NSW 2033 Australia Univ Leipzig Inst Comp Sci Leipzig Germany

We present a hardware implementation of population-based ant colony optimization (P-ACO) on field-programmable gate arrays (FPGAs). The ant colony optimization meta-heuristic is adopted from the natural foraging behavior of real ants and has been used to find good solutions to a wide spectrum of combinatorial optimization problems. We describe the P-ACO algorithm and present a circuit architecture that facilitates efficient FPGA implementations. The proposed design shows modest space requirements but leads to a significant reduction in runtime over software-based solutions. Several modifications and extensions of the basic algorithm are also presented, including the approximation of the heuristic function by a small, dynamically changing set of favorable decisions. (C) 2004 Elsevier B.V. All rights reserved.

关键词： ant colony optimization ant algorithm field-programmable gate array FPGA

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Towards deterministic FPGA reconfiguration

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2020年第2期13卷 236-253页

作者： Reis, Joao Gabriel Frohlich, Antonio Augusto Univ Fed Santa Catarina Software Hardware Integrat Lab BR-88040900 Florianopolis SC Brazil

Rigid partitioning of components in hardware/software co-design flows can lead to suboptimal choices in embedded systems with dynamic runtime requirements. FPGAs allow systems to cope with such unforeseen conditions by changing portions of hardware dynamically while other parts are still active. Nevertheless, to guarantee a transparent reconfiguration, it is necessary to ensure that it does not disrupt the timing requirements of the running tasks and vice-versa. This work proposes a deterministic FPGA reconfiguration mechanism capable of mitigating the interference generated by I/O operations occurring in parallel. The reconfiguration is confined in the idle time without interfering with or being interfered by other activities occurring in the system, including peripherals performing I/O. The scheme decomposes the reconfiguration process in small steps such that it is preemptable, and compliant with timing requirements. To quantify the impact of I/O interference on FPGA reconfiguration, we measured the execution time to load bitstreams from memory to the FPGA reconfiguration interface with multiple peripherals performing I/O in parallel. Results show that if the I/O interference is not taken into account and mitigated, the reconfiguration time can grow up to 8,800% when peripherals are performing I/O operations through DMA.

关键词： field-programmable gate array FPGA dynamic reconfiguration I/O interference embedded systems partial reconfiguration power management interference mitigation speculative reconfiguration operating system

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A real-time FPGA accelerated stream processing for hyperspectral image classification

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GEOCARTO INTERNATIONAL 2022年第1期37卷 52-69页

作者： Gyaneshwar, Dubacharla Nidamanuri, Rama Rao Indian Inst Space Sci & Technol Remote Sensing Lab Dept Earth & Space Sci Thiruvananthapuram 695547 Kerala India

Realizing real-time classification of hyperspectral imagery has attracted researchers across various scientific and engineering disciplines. Several time-critical applications of high-resolution hyperspectral imaging require analysis of hyperspectral imagery with minimal turnaround time. In this regard, field-programmable gate arrays (FPGAs) provide cost-effective performance over the other high-performance reconfigurable computing systems. Developing such efficient systems poses several technical challenges such as designing and validating the FPGA architecture. A rapid prototyping approach offers several benefits in designing and developing FPGA architectures. This paper proposes a rapid prototyping method for the design and implementation of a multi-class support vector machine (MSVM) algorithm for real-time hyperspectral imagery classification using a low-cost FPGA system. We have evaluated design performance in terms of overall accuracy, resource utilization as well as timing requirements using four different datasets containing airborne, drone, and ground-based hyperspectral imagery. Experimental results show that the proposed FPGA design performs classification under strict real-time constraints.

关键词： Hyperspectral imagery real-time processing field-programmable gate array rapid prototyping multi-class support vector machine

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FPGA and ASIC realisation of EMD algorithm for real-time signal processing

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IET CIRCUITS DEVICES & SYSTEMS 2020年第6期14卷 741-749页

作者： Das, Kaushik Nath, Debanjali Pradhan, Sambhu Nath Natl Inst Technol Elect & Commun Engn Dept Agartala India

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead of using separate modules for each calculation. In this work, the traditional cubic spline interpolation has been replaced with sawtooth transform followed by a smoothing module called moving average. In this study firstly, Verilog-HDL code for the EMD is written using Xilinx Vivado and tested in the simulation phase, later dumped into Digilentinc Basys 3 FPGA board to do the hardware verification. For ASIC, the code is synthesised using Cadence Genus tool with the semi-conductor laboratory 180 nm cell library and the layout is made in the Cadence Innovus tool. The proposed EMD can work with a clock/sampling rate up to 25 MHz and has a layout area of 3.9 mm(2). For the reduction of power consumption of the overall system, clock gating has been used which helps to reduce the dynamic power of the modules, when they are not in use.

关键词： application specific integrated circuits hardware description languages interpolation field programmable gate arrays splines (mathematics) integrated circuit design signal processing Hilbert transforms logic design mathematics computing ASIC EMD algorithm real-time signal processing empirical mode decomposition algorithm traditional cubic spline interpolation smoothing module Verilog-HDL code Digilentinc Basys 3 FPGA board semiconductor laboratory cell library field-programmable gate array application specific integrated circuit sawtooth transform Xilinx Vivado simulation phase hardware verification Cadence Genus tool Cadence Innovus tool power consumption reduction clock gating dynamic power reduction moving average size 180 0 nm frequency 25 0 MHz

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Experimental and numerical investigations on amalgamation of mixed frequency carrier based asymmetrical 15 level multilevel inverter

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ELECTRICAL ENGINEERING 2024年 1-15页

作者： Paramasivan, Muthukumar Prasad, T. Narasimha Vanchinathan, K. Saveetha Inst Med & Tech Sci Saveetha Sch Engn Dept Elect & Elect Engn Chennai 602105 Tamilnadu India Dept Elect & Elect Engn Chirala Andhra Prades India Velalar Coll Engn & Technol Dept Elect & Elect Engn Erode 638012 Tamilnadu India

This research encompasses the investigations of a multicarrier based 15 level multilevel inverter in an asymmetrical mode. The series connection of three voltage sources (12 V, 24 V and 48 V) with three metal oxide semiconductor field effect transistor (MOSFET) switches and a parallel H-bridge are used to construct the multilevel inverter. The phase disposition configurations of triangle carrier and inverted sine carrier are selected for the investigations. The indigenous pulse-width modulation (PWM) has been generated for three series switches from the comparison of seven carriers with a reference. The two frequencies (1 kHz and 4 kHz) are chosen for carriers. The 4 kHz frequency carrier will be active only at the peak of the sine reference between 5 pi/12 >= theta <= 7 pi/12 in positive half cycle and between 17 pi/12 >= theta <= 19 pi/12 in negative half cycle, remaining period 1 kHz frequency carrier has been active. These schemes have been verified with single-phase MLI with RL load. The MATLAB-based simulation results of fours schemes are presented. A field-programmable gate array-based experimental result of best scheme among four is reported, and corresponding hardware results are evidenced. The Xilinx Vivado design suite has been used for design synthesis and bit file generation for the FPGA.

关键词： Multicarrier Multilevel inverter Pulse-width modulation Total harmonic distortion field-programmable gate array

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A simple and improved digital timing method for positron emission tomography

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2010年第1期622卷 219-224页

作者： Hu, Wei Choi, Yong Hong, Key Jo Kang, Jihoon Jung, Jin Ho Huh, Youn Suk Lim, Hyun Keong Kim, Sang Su Min, Byung Jun Kim, Byung-Tae Sogang Univ Dept Elect Engn Seoul 121742 South Korea Sungkyunkwan Univ Samsung Med Ctr Dept Nucl Med Sch Med Seoul 135710 South Korea

A simple and improved digital timing method was developed for positron emission tomography (PET). This method, the so-called 'initial rise interpolation method', is based on an important characteristic of gamma signals: a properly pre-amplified and sampled gamma signal pulse can be characterized to arrive with an initial rise from the baseline and then reach a maximum rise. The pulse arrival time was obtained by calculating the intersection of the initial rise line with the baseline for each gamma signal pulse. Using an 8-channel 100 MHz free-running ADC and FPGA combined data acquisition (DAQ) card, three digital timing methods were employed to measure the coincidence timing resolution of two types of recently developed 3 mm x 3 mm PET sensors (a fast and a slow CARD). The results showed that the initial rise interpolation method provides the best timing resolution for both types of GAPDs: 0.7 ns FWHM for fast GAPD and 1.5 ns FWHM for slow GAPD (digital CFD: 1.5 and 2.2 ns FWHM;maximum rise interpolation: 1.8 and 2.7 ns FWHM). By implementing the initial rise interpolation method into the FPGA of DAQ card, PET images of two F-18 line sources were acquired successfully using a pair of 4x4 GAPD-LYSO array detectors (single pixel size: 3 mm x 3 mm). The acquired image spatial resolution was a 3.1 mm FWHM. Furthermore, the simulation was performed to evaluate the effects of the pulse rise time, pulse amplitude and front-end noise level on the timing resolution estimated using the three digital timing methods. In accordance with the measurement results, the simulation results also showed that the initial rise interpolation method provided the best timing resolution. These results show that this simple and improved digital timing method is reliable and useful for the development of high performance PET. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Positron emission tomography Digital timing method field-programmable gate array Geiger mode avalanche photodiode (GAPD)

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FPGA implementations of scale-invariant models of neural networks

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第6期24卷 5090-5099页

作者： Zhanabaev, Zeinulla Kozhagulov, Yeldos Zhexebay, Dauren al Farabi Kazakh Natl Univ Fac Phys & Technol Dept Solid State Phys & Nonlinear Phys Alma Ata Kazakhstan

Integrated circuit implementations of new models of neural networks with scale-invariant properties are presented. The specifics of such models are necessary in analysis of discrete mappings containing fractional power. We suggest an algorithm for increasing the power of a physical value by using a field-programmable gate array (FPGA). Comparisons between FPGA implementations and numerical results are demonstrated.

关键词： Neural networks field-programmable gate array digital scheme scale invariance

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architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2020年第2期28卷 516-529页

作者： Li, He Davis, James J. Wickerson, John Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

Many algorithms feature an iterative loop that converges to the result of interest. The numerical operations in such algorithms are generally implemented using finite-precision arithmetic, either fixed- or floating-point, most of which operate least-significant digit first. This results in a fundamental problem: if, after some time, the result has not converged, is this because we have not run the algorithm for enough iterations or because the arithmetic in some iterations was insufficiently precise? There is no easy way to answer this question, so users will often over-budget precision in the hope that the answer will always be to run for a few more iterations. We propose a fundamentally new approach: with the appropriate arithmetic able to generate results from most-significant digit first, we show that fixed compute-area hardware can be used to calculate an arbitrary number of algorithmic iterations to arbitrary precision, with both precision and approximant index increasing in lockstep. Consequently, datapaths constructed following our principles demonstrate efficiency over their traditional arithmetic equivalents where the latter's precisions are either under- or over-budgeted for the computation of a result to a particular accuracy. Use of most-significant digit-first arithmetic additionally allows us to declare certain digits to be stable at runtime, avoiding their recalculation in subsequent iterations and thereby increasing performance and decreasing memory footprints. Versus arbitrary-precision iterative solvers without the optimizations we detail herein, we achieve up-to 16x performance speedups and 1.9 x memory savings for the evaluated benchmarks.

关键词： Arbitrary-precision arithmetic hardware architecture online arithmetic field-programmable gate array

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DESIGN AND OPTIMIZATION OF A HORIZONTALLY PARTITIONED, HIGH-SPEED, 3D TREE-BASED FPGA

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IEEE MICRO 2015年第6期35卷 48-59页

作者： Pangracious, Vinod Marrakchi, Zied Mehrez, Habib Univ Paris 06 Elect Engn F-75252 Paris 05 France Flexras Technol St Denis France Univ Paris 06 Syst Chip Dept F-75252 Paris 05 France

The authors explore and design the traditional field-programmable gate array (fpga) interconnect topologies and architectures that can play an important role in improving performance and density. they address long wire length issues associated with tree-based programmable interconnects using 3d design and manufacturing technologies. using their dedicated 3d design and optimization methodology, the authors show that 3d tree-based architecture is 1.5 times faster than the mesh-based counterpart.

关键词： 3D integration BFT butterfly fat tree Computer architecture Delays field programmable gate arrays field-programmable gate array FPGA Integrated circuit interconnections mesh Routing Three-dimensional displays through silicon via Through-silicon vias tree-based FPGA TSV

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An FPGA-Based Unscented Kalman Filter for System-On-Chip Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2017年第4期64卷 447-451页

作者： Soh, Jeremy Wu, Xiaofeng Univ Sydney Aerosp Mech & Mechatron Engn Sydney NSW 2006 Australia

The demand for fast and accurate state estimation in embedded systems has been increasing lately, due at least in part to mobile robotics such as an unmanned aerial vehicle (UAV). The desire to maintain high performance but with compact form factors leads to implementation issues, particularly with more complex systems. A hardware-based approach using field-programmable gate arrays may be able to alleviate these issues but tends to have a more complicated development process than traditional software-based approaches. In order to simplify development and promote portability between embedded applications, a hardware/software codesign of the unscented Kalman filter is presented. An example implementation (N = 18) of the hardware IP core only is presented using the Zynq-7000 XC7Z045 with synthesis, power, and timing results for the 1, 2, 5, and 10 processing-element cases.

关键词： Coprocessors field-programmable gate array Kalman filters nonlinear filters signal processing system-on-chip

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