In 2013 Tore Supra limiter tokamak at CFA Cadarache went through major changes to become the WEST tokamak (Tungsten [W] Environment in Steady state Tokamak). The tokamak was upgraded into an X point divertor device. T...
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In 2013 Tore Supra limiter tokamak at CFA Cadarache went through major changes to become the WEST tokamak (Tungsten [W] Environment in Steady state Tokamak). The tokamak was upgraded into an X point divertor device. Taking advantage of its long discharge capability, WEST'S goal is to minimize technological and operational risks of the actively cooled tungsten divertor for ITER. At the same time, Control Data Access and Communication (CODAC) system has been redesigned in order to satisfy the performance and evolutions needed by researchers, and to facilitate maintenance and evolution for the CODAC team. This paper describes the upgrade of the CODAC system from Tore Supra to WEST.
Networked Music Performance (NMP) applications are acknowledged to be a particularly challenging field due to their stringent latency requirements and their demand for high audio quality. Most solutions developed in t...
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ISBN:
(纸本)9798350382549
Networked Music Performance (NMP) applications are acknowledged to be a particularly challenging field due to their stringent latency requirements and their demand for high audio quality. Most solutions developed in the last decades tried to overcome these obstacles by leveraging software approaches, that can introduce excessive time delays as a consequence of the general-purpose nature of the architectures on which they are implemented. Alternatively, a dedicated audio processor can be employed to minimize the mouth-to-ear latency. This paper presents the ongoing development of an hardware system that exploits an Application-Specific Instruction set Processor (ASIP) implemented on a field-programmable gate array (FPGA) to accelerate audio sample management. Specifically, a Transport Triggered Architecture (TTA) is being investigated as a processor design that aligns well with the required application domains. Preliminary empirical results indicate that the proposed solution has the potential to achieve extremely low latency, compatible with NMP requirements. Further optimizations and enhancements are actively being pursued to address the yet open challenges posed by NMP applications.
Universal Asynchronous Receiver and Transmitter (UART) is a popular asynchronous serial communication standard Although the transmission speed is not too high, UART has the advantage of simplicity, it is easy to imple...
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Universal Asynchronous Receiver and Transmitter (UART) is a popular asynchronous serial communication standard Although the transmission speed is not too high, UART has the advantage of simplicity, it is easy to implement and has low power consumption. Therefore, UART is still used in various digital modules that do not require high communication speed, such as SIM module, Bluetooth, GPS, etc. However, communication with many low-speed peripherals can reduce the efficiency of data bus usage and processor's performance. In this paper, we propose a multichannel UART design to efficiently utilise the Advanced Peripheral Bus (APB) standard data bus in order to support simultaneously multiple transmission data frames with different rates. Then, we evaluate the performance of our multichannel UART design by means of simulations and practical implementation using field-programmable gate array boards. The evaluation results show that our proposed multi-channel UART module ensures stable operation while guaranteeing proper transmission to/from multiple devices following UART standard with different configurations.
field-programmable gate array technologies are creating a new range of challenges for pervasive and ubiquitous systems. Revisiting and extending approaches borrowed from the purely software domain is a fundamental opp...
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field-programmable gate array technologies are creating a new range of challenges for pervasive and ubiquitous systems. Revisiting and extending approaches borrowed from the purely software domain is a fundamental opportunity in this scenario. In particular, this paper addresses code mobility, a well-established approach used to dynamically adapt a distributed system based on the actual application needs, and extends it to a deep code mobility concept, allowing 'logical' hardware components to be migrated across a pervasive infrastructure. The work presents the architecture and the prototype implementation of a reconfigurable computing framework providing full support to deep code mobility through an abstraction layer which exposes a portable view of the underlying reconfigurable hardware. The paper then thoroughly discusses two application scenarios, hardware-accelerated distributed data mining and autonomous online testing, confirming the impact of deep code mobility in real-world pervasive computing contexts.
Recent advances in field-programmable gate array (FPGA) technologies have made feasible the implementation of low-cost parallel computing platforms for high-performance matrix computations. Compared to conventional mu...
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Recent advances in field-programmable gate array (FPGA) technologies have made feasible the implementation of low-cost parallel computing platforms for high-performance matrix computations. Compared to conventional multiprocessor systems, the resulting multiprocessors-on-a-programmable-chip (MPoPC) can provide unique advantages and opportunities in both software and hardware. It is shown in this paper that the performance of an MPoPC can be improved dramatically by adapting slightly intellectual property (IP)-based processing elements, and customising the memory and the interconnection network. The parallel LU factorisation of large, sparse doubly-bordered block diagonal (DBBD) matrices is employed as an application example. To enhance further the performance by software techniques, a run-time load balancing strategy for this algorithm is proposed and analysed. Extensive experimental results on benchmark matrices of size up to 7,917 x 7,917 for power networks demonstrate the effectiveness of our effort.
Electrocardiogram (ECG) signals are susceptible to noise and interference from the external world. This paper presents the reduction of unwanted 50 Hz power line interference in ECG signal using multi-order adaptive L...
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Electrocardiogram (ECG) signals are susceptible to noise and interference from the external world. This paper presents the reduction of unwanted 50 Hz power line interference in ECG signal using multi-order adaptive LMS filtering. The novelty of the present method is the actual hardware implementation for power line interference removal. The design of adaptive filter is carried out by the simulink-based model and hardware-based design using FPGA. The performance measures used are signal to noise ratio (SNR), PSNR, MSE and RMSE. The novelty of the proposed method is to achieve better SNR by careful selection of the filter order using hardware.
In the modern era of the Internet of Things (IoT), especially with the rapid development of quantum computers, the implementation of postquantum cryptography algorithms in numerous terminals allows them to defend agai...
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In the modern era of the Internet of Things (IoT), especially with the rapid development of quantum computers, the implementation of postquantum cryptography algorithms in numerous terminals allows them to defend against potential future quantum attack threats. Lattice-based cryptography can withstand quantum computing attacks, making it a viable substitute for the currently prevalent classical public-key cryptography technique. However, the algorithm's significant time complexity places a substantial computational burden on the already resource-limited chip in the IoT terminal. In lattice-based cryptography algorithms, the polynomial multiplication on the finite field is well known as the most time-consuming process. Therefore, investigations into efficient methods for calculating polynomial multiplication are essential for adopting these quantum-resistant lattice-based algorithms on a low-profile IoT terminal. Number theoretic transform (NTT), a variant of fast Fourier transform (FFT), is a technique widely employed to accelerate polynomial multiplication on the finite field to achieve a subquadratic time complexity. This study presents an efficient FPGA-based implementation of number theoretic transform for the CRYSTAL Kyber, a lattice-based public-key cryptography algorithm. Our hybrid design, which supports both forward and inverse NTT, is able run at high frequencies up to 417 MHz on a low-profile Artix7-XC7A100T and achieve a low latency of 1.10 mu s while achieving state-of-the-art hardware efficiency, consuming only 541-LUTs, 680 FFs, and four 18 Kb BRAMs. This is made possible thanks to the newly proposed multilevel pipeline butterfly unit architecture in combination with employing an effective coefficient accessing pattern.
The large-area Compton camera (LACC), featuring significantly high detection sensitivity, was developed for high-speed localization of gamma-ray sources. Due to the high gamma-ray interaction event rate induced by the...
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The large-area Compton camera (LACC), featuring significantly high detection sensitivity, was developed for high-speed localization of gamma-ray sources. Due to the high gamma-ray interaction event rate induced by the high sensitivity, however, the multiplexer-based data acquisition system (DAQ) rapidly saturated, leading to deteriorated energy and imaging resolution at event rates higher than 4.7 x 103 s-1. In the present study, a new simultaneous multi-channel DAQ was developed to improve the energy and imaging resolution of the LACC even under high event rate conditions (104-106 s-1). The performance of the DAQ was evaluated with several point sources under different event rate conditions. The results indicated that the new DAQ offers significantly better performance than the existing DAQ over the entire energy and event rate ranges. Especially, the new DAQ showed high energy resolution under very high event rate conditions, i.e., 6.9% and 8.6% (for 662 keV) at 1.3 x 105 and 1.2 x 106 s-1, respectively. Furthermore, the new DAQ successfully acquired Compton images under those event rates, i.e., imaging resolutions of 13.8 degrees and 19.3 degrees at 8.7 x 104 and 106 s-1, which correspond to 1.8 and 73 mSv/hr or about 18 and 730 times the background level, respectively. (c) 2023 Korean Nuclear Society, Published by Elsevier Korea LLC. This is an open access article under the CC BY-NC-ND license (http://***/licenses/by-nc-nd/4.0/).
It will be more difficult to continue with Moore's law scaling in the next years without exploring new heterogeneous architectures with application-customised hardware. The expressive employment of customised acce...
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It will be more difficult to continue with Moore's law scaling in the next years without exploring new heterogeneous architectures with application-customised hardware. The expressive employment of customised accelerators, or runtime reconfigurable designs, will be required to deliver power- and performance-efficient systems. In view of recent technology advances, runtime partial reconfiguration has emerged supported by FPGA-based devices. Still, power consumption and performance are the principal concerns when devising new reconfigurable embedded systems. This paper addresses power and performance analysis of the partial reconfiguration process supported by runtime reconfigurable hardware. We introduce a heterogeneous system-on-chip FPGA-based runtime partial reconfigurable platform design along with an experimental and theoretical power consumption and performance models, which are specific to the partial reconfiguration process. The proposed design was implemented, and both experimental and theoretical power consumption and performance analyses were performed, thus providing a formal tool to the decision-making process between power consumption and performance applicable to the runtime reconfiguration phase. Results show an average accuracy of 89.76% for the power consumption model and 94.82% for the performance model.
Platform chips, which are pre-designed chips possessing numerous processors, memories, coprocessors, and field-programmablegates arrays, are becoming increasingly popular. Platforms eliminate the costs and risks asso...
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Platform chips, which are pre-designed chips possessing numerous processors, memories, coprocessors, and field-programmablegates arrays, are becoming increasingly popular. Platforms eliminate the costs and risks associated with creating customized chips, but with the drawbacks of poorer performance and energy consumption. Making platforms highly configurable, so they can be tuned to the particular applications that will execute on those platforms, can help reduce those drawbacks. We discuss the trends leading embedded system designers towards the use of platforrns instead of customized chips. We discuss UCR research in designing highly configurable platforms, highlighting some of our work in highly configurable caches, and in hardware/software partitioning. (C) 2003 Elsevier Ltd. All rights reserved.
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