Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in ...
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Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 mu s) for typical configuration parameters.
This introduction to the special section on Reconfigurable Computing briefly discusses the history and current state of the field and introduces the articles in the special section. [ABSTRACT FROM AUTHOR]
This introduction to the special section on Reconfigurable Computing briefly discusses the history and current state of the field and introduces the articles in the special section. [ABSTRACT FROM AUTHOR]
Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable ...
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Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.
A design of Ethernet adapter for visible light communication (VLC) is proposed in this paper. Based on field-programmable gate array (FPGA) technology and Ethernet protocols, the design applies Ethernet to VLC channel...
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A design of Ethernet adapter for visible light communication (VLC) is proposed in this paper. Based on field-programmable gate array (FPGA) technology and Ethernet protocols, the design applies Ethernet to VLC channel, enabling two-way transmission between both channels, giving solution to the conversion of signal between different coding formats. 8B10B DC-balanced encoding/decoding is used for VLC transceivers to ensure reliable and stable communication. At 1000BASE-T duplex mode, the maximum real-time net data rate on the VLC channel is 300Mbps by sending and receiving Ethernet frames in point-to-point communication with optical transceivers using phosphorescent white light emitting diode (WLED).
A field-programmable gate array-based reconfigurable parallel computing unit to calculate the Walsh-Hadamard transform is proposed. The architecture can process long-duration signals with a large number of samples. Ob...
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A field-programmable gate array-based reconfigurable parallel computing unit to calculate the Walsh-Hadamard transform is proposed. The architecture can process long-duration signals with a large number of samples. Obtained results demonstrate its versatility and usefulness in applications requiring online digital signal processing, utilising few resources in low-cost devises as Cyclone II 2C20 and Cyclone IV EP4CE22.
In this paper, we present a novel algorithm to optimize the design of Reservoir Computing using Cellular Automata models for time series applications. Besides selecting the models' hyperparameters, the proposed al...
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In this paper, we present a novel algorithm to optimize the design of Reservoir Computing using Cellular Automata models for time series applications. Besides selecting the models' hyperparameters, the proposed algorithm particularly solves the open problem of Linear Cellular Automaton rule selection. The selection method pre-selects only a few promising candidate rules out of an exponentially growing rule space. When applied to relevant benchmark datasets, the selected rules achieve low errors, with the best rules being among the top 5% of the overall rule space. The algorithm was developed based on mathematical analysis of Linear Cellular Automaton properties and is backed by almost one million experiments, adding up to a computational runtime of nearly one year. Comparisons to other state-of-the-art time series models show that the proposed Reservoir Computing using Cellular Automata models have lower computational complexity and, at the same time, achieve lower errors. Hence, our approach reduces the time needed for training and hyperparameter optimization by up to several orders of magnitude.
Steganography methods conceal covert messages inside communicated data. field-programmable gate array (FPGA) hardware implementation provides speed, flexibility and configurability. It is extremely difficult to compar...
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Steganography methods conceal covert messages inside communicated data. field-programmable gate array (FPGA) hardware implementation provides speed, flexibility and configurability. It is extremely difficult to compare published results from different platforms and technologies. The goal of our research work is to mitigate the dependency by examining implementations from multiple FPGA platforms. The research studies the implementations of 12 spatial steganography methods using Altera and Xilinx FPGAs. The methods include mix-bit LSB, least significant bit (LSB), random LSB and texture-based algorithms. The objective of the research is to develop platform-independent resources, timing, power and energy models;to empower future steganography research. Further, the article evaluates steganography methods using typical performance metrics as well as a novel performance metric. The results suggest that the mix-bit methods exhibit good performance across most of the metrics. However, when image quality is a concern, the two-bit LSB is the front runner.
Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation d...
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Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA;meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved. (c) 2022 Korean Nuclear Society, Published by Elsevier Korea LLC. This is an open access article under the CC BY-NC-ND license (http://***/licenses/by-nc-nd/4.0/).
The tendency toward electrification of marine vessels has led the evolution of the all electric ship (AES). The harsh operating environment of the AES makes the shipboard power system (SPS) vulnerable, so a powerful m...
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The tendency toward electrification of marine vessels has led the evolution of the all electric ship (AES). The harsh operating environment of the AES makes the shipboard power system (SPS) vulnerable, so a powerful monitoring system for fault detection and localization (FDL) is essential for safe navigation. We propose a machine learning based FDL method for monitoring the system condition with the problem of imbalanced training dataset. The generative adversarial network (GAN) comprising of deep convolutional neural networks was employed to synthesize numerous valid samples. Feature extraction and selection technologies were applied to time-series signals to reduce features for monitor training. Finally, the random forest (RF) model was trained using the augmented training dataset, combining real data with generated ones by GAN, to verify the capability of the GAN-RF based FDL method. Both real training and testing data were collected from the SPS model established in PSCAD/EMTDC. The results demonstrated that the monitor could distinguish different conditions in real-time with the help of hardware implementation on the FPGA and a 99% classification accuracy was achieved with excellent anti-noise capability.
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