检索结果-内蒙古大学图书馆

Synchronization control of stochastic delayed Lotka-Volterra systems with hardware simulation

ADVANCES IN DIFFERENCE EQUATIONS 2020年第1期2020卷 1-13页

作者： Wang, Lan Dong, Yiping Xie, Da Zhang, Hao Wuxi Insitute Technol Dept Fundamental Courses Wuxi Jiangsu Peoples R China Southeast Univ Sch Math Nanjing Peoples R China China Key Syst & Integrated Circuit Co Ldt Wuxi Jiangsu Peoples R China Sun Yat Sen Univ Sch Life Sci Guangzhou Peoples R China

In this paper, the synchronization control of a non-autonomous Lotka-Volterra system with time delay and stochastic effects is studied. The purpose is to firstly establish sufficient conditions for the existence of global positive solution by constructing a suitable Lyapunov function. Some synchronization criteria are then derived by designing an appropriate full controller and a pinning controller, respectively. Finally, an example is presented to illustrate the feasibility and validity of the main theoretical results based on the field-programmable gate array hardware simulation tool.

关键词： Synchronization control Lotka-Volterra system Stochastic effects Lyapunov function field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Fundus image denoising using FPGA hardware architecture

引用

INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY 2016年第1期54卷 1-13页

作者： Fredj, Amira Hadj Ben Abdallah, Mariem Malek, Jihene Azar, Ahmad Taher Monastir Univ Elect & Microelect Lab Monastir Tunisia Benha Univ Fac Comp & Informat Banha Egypt

Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion ( SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient field-programmable gate array ( FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38x performance improvement over the original MATLAB implementation and a 1.33x performance improvement over the hardware implementation using the Xilinx System Generator tool.

关键词： SRAD filter FPGA field-programmable gate array parallel architecture retinal fundus image

来源：评论

学校读者我要写书评

暂无评论

Debugging Software for the Acquisition and Preliminary Processing of Data for a Neutron Detector with an Architecture of Two Circular Buffers

引用

JOURNAL OF SURFACE INVESTIGATION 2023年第2期17卷 455-459页

作者： Golubev, M. A. Polyushkin, A. O. Solovei, V. A. Natl Res Ctr Kurchatov Inst Petersburg Nucl Phys Inst Gatchina 188300 Russia

A technique for debugging the software of a data acquisition and preliminary processing device with a network interface for a 2D position-sensitive thermal-neutron detector with delay-line readout is described. The original software transfers data through two ring buffers. Changes are proposed in the software code to check the possibility of ring-buffer overflow. It is shown that there is no data loss in the ring buffers at input-pulse frequencies up to 1 MHz. The corresponding dead time of recording is on the order of 1 mu s.

关键词： neutron detector delay-line readout field-programmable gate array circular buffer web interface local area network data processing software hardware data transfer

来源：评论

学校读者我要写书评

暂无评论

Real-Time Demonstration of Low-Complexity Time-Domain Chromatic Dispersion Equalization 19

Real-Time Demonstration of Low-Complexity Time-Domain Chroma...

引用

19th International Conference on Transparent Optical Networks (ICTON)

作者： Martins, Celestino S. Amado, Sofia B. Ferreira, Ricardo M. Shahpari, Ali Teixeira, Antonio L. Guiomar, Fernando P. Pinto, Armando N. Univ Aveiro Dept Elect Telecommun & Informat Campus Univ Santiago P-3810193 Aveiro Portugal Inst Telecomunicacoes Campus Univ Santiago P-3810193 Aveiro Portugal Politecn Torino Dipartimento Elettron & Telecomunicaz Corso Duca Abruzzi 24 I-10129 Turin Italy

ISBN: (纸本)9781538608593

We demonstrate real-time CD equalization (CDE) for coherent optical transmission systems using a low complexity time-domain (TD) multiplierless finite-impulse response (FIR)-based equalizer, based on a field-programmable gate array (FPGA) implementation. The real-time operation is performed for a single-channel 2.5 Gb/s QPSK optical signal with a performance penalty of only similar to 0.15 dB with respect to the maximum performance. The hardware complexity is also evaluated in terms of occupation in a Virtex-6 FPGA-XC6VLX240T, revealing the high efficiency of the proposed CDE algorithm.

关键词： optical communications coherent detection digital signal processing real-time hardware implementation field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of EM Algorithm for 3D CT Reconstruction 22

FPGA Implementation of EM Algorithm for 3D CT Reconstruction

引用

22nd IEEE Annual International Symposium on field-programmable Custom Computing Machines ((FCCM)

作者： Choi, Young-kyu Cong, Jason Wu, Di Univ Calif Los Angeles Comp Sci Dept Los Angeles CA 90095 USA

ISBN: (纸本)9781479951116

Although the expectation maximization (EM)based 3D computed tomography (CT) reconstruction algorithm lowers radiation exposure, its long execution time hinders practical usage. To accelerate this process, we introduce a novel external memory bandwidth reduction strategy by reusing both the sinogram and the voxel intensity. Also, a customized computing engine based on field-programmable gate array (FPGA) is presented to increase the effective memory bandwidth. Experiments on actual patient data show that 85X speedup can be achieved over single-threaded CPU.

关键词： computed tomography customized architecture data reuse field-programmable gate array ray tracing

来源：评论

学校读者我要写书评

暂无评论

Space Vector Modulation Implementation on RTOS/FPGA Embedded System 3

Space Vector Modulation Implementation on RTOS/FPGA Embedded...

引用

3rd IEEE International Conference on Smart Systems and Technologies (SST)

作者： Ugljar, Marjan Bensic, Tin Barukcic, Marinko Fac Elect Engn Comp Sci & Informat Technol Osijek Osijek Croatia

ISBN: (纸本)9781538671894

The paper proposes a method for implementing Space Vector Modulation (SVM) on the CompactRio embedded platform. The concept of space vectors is presented and the mathematical model of the SVM is derived. A description of the CompactRio RTOS/FPGA Embedded platform is presented. A new method for analyzing and generating SVM gate control pulses is proposed. The proposed method to generate SVM pulses based on the symmetric SVM switching pattern using the clock of the FPGA processor is implemented and performance studied.

关键词： Voltage Source Inverter Space Vector Modulation Real-Time Operating System field-programmable gate array NI CompactRio

来源：评论

学校读者我要写书评

暂无评论

A hardware accelerator for edge detection in high-definition video using cellular neural networks 22

A hardware accelerator for edge detection in high-definition...

引用

45th Euromicro Conference on Software Engineering and Advanced Applications (SEAA) / 22nd Euromicro Conference on Digital System Design (DSD)

作者： Perez, Ignacio Valenzuela, Wladimir Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile

ISBN: (纸本)9781728128610

This paper presents the architecture of a hardware accelerator for a cellular neural network (CeNN) with an application to real-time edge detection on visible-range and infrared video. The accelerator features fully-pipelined processing elements (PEs) that exploit the data parallelism in the algorithm to perform an iteration of the CeNN on a stream of video data with high throughput. The memory architecture exploits the locality of reference in the CeNN, so that each PE uses only 5 line buffers to store pixel, state, and output data, thus achieving low on-chip memory utilization. Implemented on a Xilinx XC7A200T FPGA running at 245MHz, the accelerator performs edge detection on 1080p video using a single CeNN iteration with a throughput of 118 frames per second (fps), a total latency of 15.7 mu s, and 618mW of power consumption. The architecture features static reconfiguration to store built-in kernels and to add more PEs to support multiple iterations of the CeNN algorithm. More kernels can be added dynamically through a serial interface.

关键词： Hardware acceleration cellular neural network edge detection field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

BEYOND TRADITIONAL MICROPROCESSORS FOR GEOSCIENCE HIGH-PERFORMANCE COMPUTING APPLICATIONS

引用

IEEE MICRO 2011年第2期31卷 41-49页

作者： Lindtjorn, Olav Clapp, Robert G. Pell, Oliver Mencer, Oskar Flynn, Michael J. Fu, Haohuan Stanford Univ Sch Earth Sci Stanford CA 94305 USA Stanford Univ Ctr Earth & Environm Sci Sch Earth Sci Algorithm & Architecture Initiat Stanford CA 94305 USA Tsinghua Univ Ctr Earth Syst Sci Beijing Peoples R China

THE OIL AND GAS INDUSTRY IS A MAJOR USER OF HIGH-PERFORMANCE COMPUTING, AND GEOSCIENCE COMPUTATIONAL CYCLES ARE DOMINATED BY KERNELS THAT ARE RELATIVELY FEW AND WELL DEFINED. THIS PROJECT EXPLORES ACCELERATING GEOSCIENCE APPLICATIONS USING FPGA-BASED HARDWARE, OPTIMIZING THE ALGORITHM AND THE HARDWARE TO ACHIEVE MAXIMUM PERFORMANCE. THIS APPROACH CAN DELIVER SPEEDUP OF 20 TO 70 TIMES COMPARED WITH A CONVENTIONAL HPC NODE.

关键词： field-programmable gate array geosciences high-performance computing High Performance Computing macroprocessor Computer hardware field programmable gate arrays Earth sciences Speeding

来源：评论

学校读者我要写书评

暂无评论

An FPGA-Based Autofocusing Hardware Architecture for Digital Holography

引用

IEEE TRANSACTIONS ON COMPUTATIONAL IMAGING 2019年第2期5卷 287-300页

作者： Chen, Huan-Yuan Hwang, Wen-Jyi Cheng, Chau-Jern Lai, Xin-Ji Natl Taiwan Normal Univ Dept Comp Sci & Informat Engn Taipei 106 Taiwan Natl Taiwan Normal Univ Inst Electroopt Sci & Technol Taipei 106 Taiwan

A novel hardware architecture for the reconstruction of digital holograms with autofocusing is presented in this paper. The architecture is based on a novel autofocusing algorithm operating on a smaller local block located at the center of the source digital holograms. By exploiting global information contained in the local block, accurate focus distance can be computed with less computational complexities. Interval search is also adopted to further accelerate the process. The circuits for the fast autofocusing algorithm and subsequent reconstruction operations are effectively integrated in the proposed architecture. Two fast Fourier transform cores are shared by the operations for parallel computations with low area costs. The architecture is implemented by field programmable gate array, and is used as a hardware accelerator in a network on chip system for performance evaluation. Experimental results demonstrate that the proposed circuit exhibits the advantages of high speed computation, low power dissipation, accurate focus distance search, and hologram reconstruction for three-dimensional rendering applications.

关键词： Digital holography autofocusing field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Enhanced Architecture of FIR Filters Using Block Memories 13

Enhanced Architecture of FIR Filters Using Block Memories

引用

13th IFAC and IEEE Conference on programmable Devices and Embedded Systems

作者： Pristach, Marian Dvorak, Vojtech Fujcik, Lukas Brno Univ Technol FEEC Dept Microelect CS-61090 Brno Czech Republic

The paper presents an enhanced architecture of finite impulse response digital filters. The proposed architecture contains one multiply-accumulate unit and random access men-wiry to store data. The architecture utilizes serial calculation to achieve minimum requirements on area. Time architecture is suitable for implementation in application specific integrated circuits and field programmable gate arrays. The main advantages of the architecture are higher operating frequency, lower power consumption and smaller area utilization in particular cases. (C) 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Digital signal processing digital filter structures finite impulse response application specific integrated circuit field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：