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Application-specific bridging fault testing of FPGAs

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2004年第3期20卷 279-289页

作者： Tahoori, MB Northeastern Univ Dept ECE Boston MA 02115 USA

In this paper, a new technique for testing the interconnects of any arbitrary design mapped into an FPGA is presented. In this technique, only the configuration of logic blocks used in the design is changed, and the structure of the design remains unchanged. The test vector and configuration generation problem is systematically converted to a Boolean satisfiability (SAT) problem, and state of the art SAT-solvers are exploited for test vector and configuration generation. Experimental results on various benchmark circuits show that only two test configurations are required to test for all bridging faults, achieving 100% fault coverage, with respect to the fault list. Moreover, test vector and configuration generation time is less than a second for all benchmark designs.

关键词： field-programmable gate array interconnect satisfiability bridging fault

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Development of plasma control system for divertor configuration on QUEST

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FUSION ENGINEERING AND DESIGN 2013年第6-8期88卷 1074-1077页

作者： Hasegawa, M. Nakamura, K. Zushi, H. Hanada, K. Fujisawa, A. Matsuoka, K. Mitarai, O. Idei, H. Nagashima, Y. Tokunaga, K. Kawasaki, S. Nakashima, H. Higashijima, A. Kyushu Univ Appl Mech Res Inst Kasuga Fukuoka 816 Japan Tokai Univ Toro Ku Kumamoto Japan

A plasma control system to sustain divertor configurations is developed on QUEST (Q-shu university experiment with steady-state spherical tokamak). Magnetic fluxes are numerically integrated at 100 kHz using FPGA (field-programmable gate array) modules and transferred to a main calculation loop at 4 kHz. With these signals, plasma shapes are identified in real time at 2 kHz under the assumption that the plasma current can be represented as one filament current. This calculation is done in another calculation loop in parallel by taking advantage of a multi-core processor of the plasma control system. The inside and outside plasma edge positions are controlled to their target positions using PID (proportional-integral-derivative) control loops. Whereas the outside edge position can not be controlled by the outer PF coil current, the inside edge position can be controlled by the inner PF coil current. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Plasma shape identification Real-time control Divertor configuration field-programmable gate array

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HARDWARE REALIZABLE LATTICE-REDUCTION-AIDED DETECTORS FOR LARGE-SCALE MIMO SYSTEMS 22

HARDWARE REALIZABLE LATTICE-REDUCTION-AIDED DETECTORS FOR LA...

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22nd European Signal Processing Conference (EUSIPCO)

作者： Zhou, Qi Ma, Xiaoli Ratrix Technol Atlanta GA 30308 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9780992862619

Because of their lower complexity and better error performance over K-best detectors, lattice-reduction (LR)-aided K-best detectors have recently proposed for large-scale multi-input multi-output (MIMO) detection. Among existing LR-aided K-best detectors, complex LR-aided K-best detector is more attractive compared to its real counterpart due to its potential lower latency and resources. However, one main difficulty in hardware implementation of complex LR-aided K-best is to efficiently find top K children of each layer in complex domain. In this paper, we propose and implement an LR-aided K-best algorithm that efficiently finds top K children in each layer when K is relatively small. Our implementation results on Xilinx VC707 FPGA board show that, with the aid of LR, the proposed LR-aided K-best implementation can support 3 Gbps transmissions for 16x16 MIMO systems with 1024-QAM with about 2.7 dB loss to the maximum likelihood detector at bit-error rate 10(-4).

关键词： Lattice reduction large-scale MIMO K-best algorithm field-programmable gate array very-large-scale integration

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An Evaluation of Vivado HLS for Efficient System Design 58

An Evaluation of Vivado HLS for Efficient System Design

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58th ELMAR International Symposium

作者： Georgopoulos, Konstantinos Chrysos, Grigorios Malakonakis, Pavlos Nikitakis, Antonis Tampouratzis, Nikos Dollas, Apostolos Pnevmatikatos, Dionisios Papaefstathiou, Yannis Tech Univ Crete Microprocessor & Hardware Lab Khania Greece

ISBN: (纸本)9789531842211

High-Level Synthesis (HLS) tools are hailed as one of the most promising ways to bridge the design productivity gap, especially for reconfigurable systems. These tools increase designer productivity at a possible performance and/or silicon cost, although the designer can play a significant role in the minimisation of both. Currently, one of the key challenges for the designer is to efficiently use the vendor-defined methodology and the design guidelines of the HLS tool. Hence, this work aims at assisting designers in taking full advantage and making optimal use of the official HLS methodology when implementing three fundamental algorithms used in a variety of video and image processing applications. One is a sorting algorithm while the other two are algorithms used in traversing tree/graph data structures. The work presented here concerns a highly popular HLS tool, namely Vivado HLS, and the experiences and analysis of the authors helps in the efficient use of the toolset, which can significantly increase design productivity when compared to the naive datasheet-based approach;the performance of all the resulting synthesisable models is also provided for completeness.

关键词： High-Level Synthesis Reconfigurable Computing field-programmable gate array Data Structures

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High Performance FPGA Implementation of Elliptic Curve Cryptography over Binary fields 13

High Performance FPGA Implementation of Elliptic Curve Crypt...

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13th IEEE International Conference on Trust Security and Privacy in Computing and Communications (TrustCom)

作者： Liu, Shuai Ju, Lei Cai, Xiaojun Jia, Zhiping Zhang, Zhiyong Shandong Univ Sch Comp Sci & Technol Jinan Peoples R China

ISBN: (纸本)9781479965137

In this paper, we propose a high performance hardware implementation architecture of elliptic curve scalar multiplication over binary fields. The proposed architecture is based on the Montgomery ladder method and uses polynomial basis for finite field (FF) arithmetic. A single Karatsuba multiplier runs with no idle cycle significantly increases the performance of FF multiplication while spending small amount of hardware resources, and other FF operations performed in parallel with the FF multiplier. The optimized circuits lead to a lesser area requirement compared to other high performance implementations. An implementation for the National Institute of Standards and Technology (NIST) recommended curve with degree 163 is shown, the proposed design can reach 121 MHz with 10,417 slices when implemented on Xilinx Virtex-4 XC4VLX200 FPGA device, the total time required for one elliptic curve scalar multiplication is 9.0 mu s.

关键词： elliptic curve cryptography field-programmable gate array binary fields polynomial basis

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Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator 20

Optimizing Bayesian Recurrent Neural Networks on an FPGA-bas...

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20th International Conference on field-programmable Technology (ICFPT)

作者： Ferianc, Martin Que, Zhiqiang Fan, Hongxiang Luk, Wayne Rodrigues, Miguel UCL Dept Elect & Elect Engn London England Imperial Coll London Dept Comp London England

ISBN: (纸本)9781665420105

Neural networks have demonstrated their outstanding performance in a wide range of tasks. Specifically recurrent architectures based on long-short term memory (LSTM) cells have manifested excellent capability to model time dependencies in real-world data. However, standard recurrent architectures cannot estimate their uncertainty which is essential for safety-critical applications such as in medicine. In contrast, Bayesian recurrent neural networks (RNNs) are able to provide uncertainty estimation with improved accuracy. Nonetheless, Bayesian RNNs are computationally and memory demanding, which limits their practicality despite their advantages. To address this issue, we propose an FPGA-based hardware design to accelerate Bayesian LSTM-based RNNs. To further improve the overall algorithmic-hardware performance, a co-design framework is proposed to explore the most fitting algorithmic-hardware configurations for Bayesian RNNs. We conduct extensive experiments on healthcare applications to demonstrate the improvement of our design and the effectiveness of our framework. Compared with GPU implementation, our FPGA-based design can achieve up to 10 times speedup with nearly 106 times higher energy efficiency. To the best of our knowledge, this is the first work targeting acceleration of Bayesian RNNs on FPGAs.

关键词： Recurrent neural networks Bayesian inference field-programmable gate array Hardware acceleration

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Optical Transceiver with Deficit Round Robin and RS232 Interface for Synchronous Optical Networking

Optical Transceiver with Deficit Round Robin and RS232 Inter...

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IEEE International Conference on Systems, Man, and Cybernetics (SMC)

作者： Sung, Guo-Ming Chou, Wen-Duen Chiu, Tzu-Hsuan Natl Taipei Univ Technol Dept Elect Engn Taipei Taiwan

ISBN: (纸本)9781509018970

This paper presents an optical transceiver, whose packet process is completed with deficit round robin (DRR) and RS232 interface, for optical synchronous optical networking (SONET) which can service on both asymmetric digital subscriber line (ADSL) and optical packet switching (OPS). To resolve the clock jitter, not only the cycle decision but also the reset function are used to synchronize the clock waveform. In the proposed DRR, it performs the packet process with low delay and low loss. Moreover, the RS232 interface, which is integrated with the field-programmable gate array (FPGA) board, is adopted due to its easy implementation. The processing data will be queued with DRR and be sent to electrical/optical (E/O) converter from the RS232 port on FPGA board (Transmitter). Passing through the optical fiber, the packet from transmitter is sent to the O/E converter and then received at the RS232 port on another FPGA board. The received electrical packet will be displayed on the seven-segment display of FPGA board to verify the transceiver function for SONET. Note that the proposed architecture is designed with Verilog hardware describe language (Verilog HDL). According to the measured results, the data transfer rate is 115,200 bps with the FPGA operating frequency of 50 MHz and the fiber distance of 5 km.

关键词： defict round robin RS232 interface transceiver synchronous optical netwoking asymmetric digital subscriber line hardware describe language field-programmable gate array

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A digital architecture for striping noise compensation in push-broom hyperspectral cameras 38

A digital architecture for striping noise compensation in pu...

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Conference on Applications of Digital Image Processing XXXVIII

作者： Valenzuela, Wladimir E. Figueroa, Miguel Pezoa, Jorge E. Meza, Pablo Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Ctr Opt & Photon Concepcion Chile Univ La Frontera Dept Elect Engn Temuco Chile

ISBN: (纸本)9781628417654

We present a striping noise compensation architecture for hyperspectral push-broom cameras, implemented on a field-programmable gate array (FPGA). The circuit is fast, compact, low power, and is capable of eliminating the striping noise in-line during the image acquisition process. The architecture implements a multi dimensional neural network (MDNN) algorithm for striping noise compensation previously reported by our group. The algorithm relies on the assumption that the amount of light impinging at the neighboring photo-detectors is approximately the same in the spatial and spectral dimensions. Under this assumption, two striping noise parameters are estimated using spatial and spectral information from the raw data. We implemented the circuit on a Xilinx ZYNQ XC7Z2010 FPGA and tested it with images obtained from a NIR N17E push-broom camera, with a frame rate of 25fps and a band-pixel rate of 1.888 MHz. The setup consists of a loop of 320 samples of 320 spatial lines and 236 spectral bands between 900 and 1700 nanometers, in laboratory condition, captured with a rigid push-broom controller. The noise compensation core can run at more than 100 MHZ and consumes less than 30mW of dynamic power, using less than 10% of the logic resources available on the chip. It also uses one of two ARM processors available on the FPGA for data acquisition and communication purposes.

关键词： striping noise compensation custom hardware architecture field-programmable gate array FPGA hardware/software codesign neural network

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Convolutional neural networks of the YOLO class in computer vision systems for mobile robotic complexes

Convolutional neural networks of the YOLO class in computer ...

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International Siberian Conference on Control and Communications (SIBCON)

作者： Zoev, Ivan V. Beresnev, Alexey P. Markov, Nikolay G. Tomsk Polytech Univ Dept Informat Technol Tomsk Russia

ISBN: (纸本)9781538651421

An important scientific direction is the development and study- of computer vision systems (CVS) for mobile robotic complexes. Today, developers of CVS are most often using convolutional neural networks (CNN). For increasing the speed detection of objects on images in CVS, there has been a trend of using CNN, which are hardware-implemented on field programmable gate array (FPGAs). This article shows that the perspective for hardware implementation on the FPGA is the tiny-YOLO (_:NN from the YOLO class. For reduce required FPGA computing resources in this (_:NN, was proposed to use Inception-ResNet modules. We was found that with high detection accuracy of objects in images with minimum resources requirements provide by the tiny-YOLO-InceptionResNet2 network architecture. It is obtained from replacing the fifth tiny-YOLO convolutional layer of the tiny-YOLO CNN with two sequential processing Inception-ResNet 'nodules. Also results of the study of the detection accuracy of objects using the CNN for this architecture with the lack of resource-intensive operations: batch normalization and bias from calculations were given. These studies were performed for different formats of representation numbers in the FPGA.

关键词： mobile robotic systems computer vision systems object detection on images convolutional neural networks field-programmable gate array

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The RF Amplifier Remote Monitoring System Based on Gigabit Ethernet

The RF Amplifier Remote Monitoring System Based on Gigabit E...

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4th International Conference on Manufacturing Science and Engineering (ICMSE 2013)

作者： Bao Jilong An Peng Ningbo Univ Technol Sch Elect & Informat Engn Ningbo 315016 Zhejiang Peoples R China

ISBN: (纸本)9783037856932

Based on the Gigabit Ethernet Protocol, the RF (Radio Frequency) power amplifier remote monitoring system was designed. The system collect digital signal from predistortion module, transmit the gigabit Ethernet network to outside, and improve the system efficiency. It adopts the SOPC technology hardcore and softcore, which makes the whole system realized in the single piece of chip. Softcore is the Altera's IF core-Nios II processor, design processors, make use of the custom parts and programs gigabit Ethernet transceiver and internal driving in processor. The integration and reliability of the system are in great improvement. Through testing, system function can satisfy transmission requirements of normal transceiver RF power amplifier state information and control information.

关键词： Power Amplifier Gigabyte Ethernet Remote Monitoring field-programmable gate array

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