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Design of exact reduct rough set hardware accelerator for early-stage diabetes risk prediction

RESULTS IN CONTROL AND OPTIMIZATION 2024年 14卷

作者： Tiwari, Kanchan S. Dattasamje, Uma D. Kadam, Rekha S. Dudhedia, Manisha A. Andhale, Aishwarya A. Pansare, Jayshree R. Marlapalle, Bapurao G. SP Pune Univ MES Coll Engn Dept Elect & Telecommun Engn Pune Maharashtra India Marathwada Mitra Mandals Coll Engn Dept Elect & Telecommun Pune India MKSSSs Cummins Coll Engn Women Dept Informat Technol Pune Maharashtra India SP Pune Univ MES Coll Engn Dept Comp Engn Pune Maharashtra India Deogiri Inst Engn & Management Studies Dept Mech Engn Chh Sambhajinagar 431005 India

Diabetes is a prevalent, chronic metabolic disorder worldwide. Detecting and predicting risks early are vital for timely intervention. In this paper, the design and implementation of an Exact Reduct Rough Set Hardware Accelerator is presented for early-stage diabetes risk prediction. The proposed hardware accelerator leverages the principles of Rough Set theory to identify essential features or attributes (reducts) from a large dataset that effectively predict the risk of diabetes at an early stage. The architecture of the hardware accelerator is optimized to efficiently handle large datasets commonly encountered in medical applications. It includes modules for data preprocessing, discernibility, matrix computation, and reduct determination. The proposed design is implemented on SPARTAN -6 field programmable gate array;it works on 100 MHz and supports 3 stages pipelining. The extensive experimentation, employing a comprehensive dataset of diabetes patients, unequivocally demonstrates the hardware accelerator's superior performance compared to traditional methods and software-based implementations. The Exact Reduct Rough Set Hardware Accelerator provides a powerful tool for medical professionals to identify patients at risk early on, enabling timely interventions and personalized care to improve patient health outcomes. The proposed accelerator contributes to the growing field of medical decision support systems and holds promise for broader applications in healthcare and beyond. The findings from this study can be seamlessly incorporated into the system-on-chip platform, contributing to the creation of intelligent tools for monitoring and managing diabetes. By offloading rough set computations to hardware accelerators on the wearable device, the data does not need to be continuously transmitted to external servers for analysis, ensuring user privacy and reducing communication overhead.

关键词： Exact reduct field-programmable gate array Hardware accelerator Rough set modules Discernibility matrix Classification Rules HDL and SPARTAN 6

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Real-Time Variation Mapping for parametric defect localization on ICs. Proof of concept, improvements, and application to new parameters

Real-Time Variation Mapping for parametric defect localizati...

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IEEE International Reliability Physics Symposium (IRPS)

作者： Saury, L. Cany, S. ST Ericsson Failure Anal Lab F-38019 Grenoble France

ISBN: (纸本)9781457716799

Localization of parametric defects on Analog / Mixed Signal and RF devices remains a challenge today. A very promising dynamic technique to address this issue is the parametric Variation Mapping (xVM) under Thermal Laser Stimulation (TLS). In this paper, we stress the importance of high-speed integrated solution for an efficient xVM implementation, which leads to the concept of Real-Time Variation Mapping (RTVM). Two concrete FPGA-based RTVM solutions are described and validated on Analog and RF case studies. Detailed results are presented and new developments are introduced.

关键词： real-time variation mapping field-programmable gate array fault isolation parametric defects

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FPGA-based Fractional Brownian Motion Signal-Patterns for Optical Packet Generation

FPGA-based Fractional Brownian Motion Signal-Patterns for Op...

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2006 International Telecommunications Symposium (ITS)

作者： Loss, G. Coelho, R. IME Dept Elect Engn Lab Res Opt Syst Commun Rio De Janeiro Brazil

ISBN: (纸本)9781424436446

Signal-pattern generation with different distributions and statistical parameters is an important issue for optical communications performance evaluation. This generation must include the signals' scaling or time-dependence degree representation. This paper proposes a new field-programmable gate array (FPGA)-based architecture to generate signals with fractional Brownian motion (fBm) patterns. The proposed implementation enables real-time performance experiments for optical communications using an Altera's Stratix Device Family. Uniform and a Gaussian sample generations were also implemented in this paper. The FPGA blocks were validated considering a real H.263 encoded video sequence. The experiments show that the proposed fBm block architecture well-fitted the statistical parameters of the real video sequence and the fBm pattern. The proposed solution also presents an interesting trade-off between FPGA device resources usage and a maximum clock frequency.

关键词： optical pattern generation optical packet switching field-programmable gate array fBm processes Hurst parameter

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An Implementation of Voice Recognition and Control System for Electric Equipment 4

An Implementation of Voice Recognition and Control System fo...

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4th International Symposium on Computer, Consumer and Control (IS3C)

作者： Tsai, Wen-Chung Lian, Yu-Ruei Hsu, Shih-Hung Zheng, Qi-Xun Su, Yu-Chen Chen, Jia-Xian Chaoyang Univ Technol Dept Informat & Commun 168 Jifeng E Rd Taichung 41349 Taiwan

ISBN: (纸本)9781538670361

In this paper, we propose a novel control method using voice recognition for electric equipment. By doing so, users can just make voice to control the targeted machine and use without any hand-held device. Especially, the implemented system is based on a FPGA (field-programmable gate array) embedded system, that provides a capability to enhance the performance of signal processing by employing specific hardware-accelerated co-processors. As such, a more intelligent and performance effective control style will be realized for future smart control of electric equipment.

关键词： Electric Equipment Embedded System field-programmable gate array Signal Processing Voice Recognition

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2014 International Symposium on Computer Architecture Influential Paper Award

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IEEE MICRO 2014年第6期34卷 94-95页

作者： Keckler, Stephen W. Nvidia University of California San Diego

This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper 'PipeRench: A Coprocessor for Streaming Mul... 详细信息

关键词： Awards field-programmable gate array FPGA influential paper award ISCA Maurice Wilkes Award PipeRench Ravi Rajwar reconfigurable logic virtualization

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Application-specific processor architecture: Then and now

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第1-2期53卷 197-215页

作者： Cappello, Peter Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasingly similar to those of systolic arrays. We then describe some economic and technological forces that are changing the landscape of architectural research. At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability. We describe a 2D architectural taxonomy, identifying what, we believe, to be a "sweet spot" for architectural research.

关键词： application-specific processor computer architecture field-programmable gate array FPGA general-purpose processor processor array systolic array taxonomy

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GRANT: Ground-Roaming Autonomous Neuromorphic Targeter

GRANT: Ground-Roaming Autonomous Neuromorphic Targeter

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International Joint Conference on Neural Networks (IJCNN) held as part of the IEEE World Congress on Computational Intelligence (IEEE WCCI)

作者： Ambrose, Jonathan D. Foshie, Adam Z. Dean, Mark E. Plank, James S. Rose, Garrett S. Mitchell, J. Parker Schuman, Catherine D. Bruer, Grant Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA Oak Ridge Natl Lab POB 2009 Oak Ridge TN 37830 USA Georgia Inst Technol Sch Computat Sci & Engn Atlanta GA 30332 USA

ISBN: (纸本)9781728169262

In this work we describe the design, implementation, and testing of the first neuromorphic robot capable of obstacle avoidance, grid coverage, and targeting controlled by the second generation Dynamic Adaptive Neural Network array (DANNA2) digital spiking neuromorphic processor. The simplicity of the DANNA2 processor along with the TENNLab hardware/software co-design framework allows for compact spiking networks that can run efficiently on a small, resource-constrained, platform such as a Xilinx Artix-7 field-programmable gate array. Additionally, we present the dynamic reconfigurability of DANNA2 arrays as a method of realizing complex, multi-objective tasks on hardware that is restricted to relatively small networks.

关键词： Autonomous Robots field-programmable gate array Neural Network Hardware Neuromorphic Recurrent Spiking Neural Networks Robot Control

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End-to-End Adaptive Packet Aggregation for High-Throughput I/O Bus Network Using Ethernet 22

End-to-End Adaptive Packet Aggregation for High-Throughput I...

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22nd IEEE Annual Symposium on High-Performance Interconnects (HOTI)

作者： Suzuki, Jun Hayashi, Yuki Kan, Masaki Miyakawa, Shinya Yoshikawa, Takashi NEC Corp Ltd Green Platform Res Labs Tokyo Japan

ISBN: (纸本)9781479958603

Input/output (I/O) bus networks using Ethernets transfer a PCI Express (PCIe) I/O packet between a host and an I/O device by encapsulating it into an Ethernet frame. Because the size of PCIe packets is generally small in such systems, the overhead to individually encapsulate them into Ethernet frames lowers the PCIe throughput provided by Ethernet connections. This decrease in throughput directly degrades the performance of I/O devices, which transmit high-throughput PCIe traffic. Examples of such devices include PCIe solid-state drives and graphics processing units. We propose a method of aggregating multiple PCIe packets into a single Ethernet frame in an end-to-end manner to provide a high-throughput PCIe connection. The aggregation is performed at the bottleneck-link rate of the Ethernet path through which those packets are transferred. The number of aggregated PCIe packets is adaptively determined by aggregating ones that reside in a transmission queue when it is scheduled to transmit packets. This enables low-latency throughput enhancement because the proposed method does not increase the transmission latency of PCIe packets by waiting for more packets to aggregate. In addition, it does not require individual configuration of operation parameters, such as aggregation threshold and time out value, depending on the rate of the PCIe traffic of I/O devices. We implemented our method in a PCIe-to-Ethernet bridge prototype using a field-programmable gate array. As a result, I/O performance improved up to 41%.

关键词： field programmable gate arrays graphics processing units local area networks telecommunication links telecommunication traffic Ethernet Ethernet frames PCI express I-O packet PCIe packets PCIe solid-state drives PCIe-to-Ethernet bridge prototype bottleneck-link rate end-to-end adaptive packet aggregation field-programmable gate array high-throughput I-O bus network high-throughput PCIe traffic low-latency throughput enhancement transmission queue Adaptive systems Aggregates Bridges Encapsulation Performance evaluation Standards Throughput field programmable gate arrays Ethernet networks Packet IO Graphics Processing Unit Telecommunication links Throughput Local Area Networks Adaptive systems telecommunication traffic bridges Performance Evaluation encapsulation Bus networks end-to-end

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Application of Polyphase Filter Banks to Wideband Monitoring Tasks

Application of Polyphase Filter Banks to Wideband Monitoring...

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IEEE North West Russia Young Researchers in Electrical and Electronic Engineering Conference (ElConRusNW)

作者： Kaplun, D. I. Klionskiy, D. M. Voznesenskiy, A. S. Gulvanskiy, V. V. St Petersburg Electrotech Univ LETI Dept Comp Sci St Petersburg 197376 Russia

ISBN: (纸本)9781479925940

The present paper discusses wideband monitoring and application of polyphase digital filter banks to dealing with practical tasks in this field. Various ways of classifying digital filter banks are provided including uniform DFT-modulated filter banks (direct and polyphase forms) and we also compare these banks by their performance. A particular polyphase filter bank with given characteristics is investigated in the time and frequency domains. Experimental research illustrates influence of white Gaussian noise on the quality of signal detection in filter bank channels. Experiments have been carried out on the basis of computer simulation in MATLAB and signal generation with the help of functions from standard MATLAB toolboxes. Experimental results contain plots of error of the first and second kinds versus signal-to-noise ratio at the input of a filter bank. Issues of polyphase filter bank implementation using CPU and CUDA are also considered in the paper.

关键词： wideband monitoring filter bank direct form polyphase form DFT-modulated filter bank field-programmable gate array CPU CUDA MATLAB

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Heavy-hitter detection using a hardware sketch with the Countmin-CU algorithm 21

Heavy-hitter detection using a hardware sketch with the Coun...

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21st Euromicro Conference on Digital System Design (DSD)

作者： Saavedra, Antonio Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Dept Comp Sci Concepcion Chile Ctr Biotechnol & Bioengn CeBiB Santiago Chile

ISBN: (纸本)9781538673768

We present a custom hardware architecture for fast heavy hitter detection in large data streams. The architecture probabilistically estimates the frequency of each element in the data stream using the Countmin-CU sketch with the H3 family of hash functions. The sketch is stored in on-chip memory, and the architecture exploits the parallelism available in the data by simultaneously processing each row of the sketch. The hash functions map each element to a set of counters on the sketch, and the sketch increments the counters that hold the minimum value, which corresponds to the estimated frequency of the element. The hash functions and sorting network are implemented in hardware as fully pipelined circuits, in order to maximize their operating clock frequency. We show a prototype of the architecture running on a Xilinx Kintex-7 XC7K325T FPGA operating with a 300MHz clock, which can process a stream of 3,982,496 32-bit elements and detect the heavy hitters with an 4x16,384-element sketch in 13.27ms, achieving a speedup of 768 compared to a modern desktop computer.

关键词： Heavy hitter streaming algorithm hardware acceleration field-programmable gate array

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