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20th International Conference on Transparent Optical Networks (ICTON)

作者： Sun, Xiaole Djordjevic, Ivan B. Univ Arizona Dept Elect & Comp Engn 1230 E Speedway Blvd Tucson AZ 85721 USA

ISBN: (纸本)9781538666050

We propose a rate-adaptive forward error correction (FEC) scheme based on spatially-coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes with its field-programmable gate array (FPGA) architecture. By FPGA emulation, we show that, with comparable computational complexity, the proposed LDPC codes provide larger coding gain and smaller error floor compare to the QC-LDPC base code. As a result, due to its hardware friendly structure, they are presented to be a promising candidate for the next-generation intelligent optical communication systems such as long-haul optical transmission system.

关键词： forward error correction LDPC field-programmable gate array spatially coupling LDPC

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Low Cost Resilient Regular Expression Matching on FPGAs 29

Low Cost Resilient Regular Expression Matching on FPGAs

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29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

作者： Leipnitz, Marcos T. de Souza, Eduardo Nunes Nazar, Gabriel L. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781509036233

The Network Function Virtualization (NFV) paradigm promises to make networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, field-programmable gate arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for FPGAs, soft errors on the configuration memory are a significant dependability threat. Therefore, in this work we evaluate the effects of configuration faults on the functionality of FPGA-based regular expression matching engines and propose fault tolerance mechanisms to improve its resilience against such faults.

关键词： Network Function Virtualization field-programmable gate array Regular Expression Matching Fault Tolerance

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Velocity measurement by a vision sensor

Velocity measurement by a vision sensor

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IEEE International Conference on Computational Intelligence for Measurement Systems and Applications

作者： Malki, Suleyman Deepak, G. Mohanna, Vincent Ringhofer, Markus Spaanenburg, Lambert Lund Univ Dept Informat Technol S-22100 Lund Sweden

ISBN: (纸本)9781424402441

Vision sensors are of increasing interest for nonintrusive, remote measurements in industrial as well as consumer products. Their operation is based on intelligent techniques for image understanding, followed by robust quantification of the detected phenomenon. A well-known application area is movement detection and isolation. This paper discusses how movement can be detected and quantified by means of a single Cellular Neural Network, implemented as a Network-on-Chip and realized on a field-programmable gate-array. The final prototype can isolate a moving object and measure its velocity at a speed of 250 frames per second.

关键词： text recognition image understanding cellular neural network embedded system field-programmable gate array

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Hardware Architectures for Computing 8-Point Cosine Number Transform

Hardware Architectures for Computing 8-Point Cosine Number T...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： de Oliveira Neto, Jose R. Lima, Juliano B. Univ Fed Pernambuco Dept Elect & Syst Recife PE Brazil

ISBN: (纸本)9781538648810

The cosine number transform (CNT) is a cosine-like number-theoretic transform, which has been employed as the basis for multimedia security schemes. In this paper, we propose hardware architectures for computing an 8-point CNT. The architectures include a pipelined approach and are based on a recently introduced fast algorithm, which has been demonstrated to be more efficient than the direct computation of the CNT. We quantify such an efficiency by considering several aspects inherent to modular arithmetic and comparing metrics obtained from field-programmable gate array (FPGA) implementations of the proposed architectures.

关键词： Number-theoretic transforms cosine number transform hardware architectures pipeline field-programmable gate array

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Wireless energy-harvesting circuit and system with error-correction ASK demodulator for body sensor network with ultra-high-frequency RFID healthcare system

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IET WIRELESS SENSOR SYSTEMS 2018年第1期8卷 36-44页

作者： Lee, Shuenn-Yuh Chen, Tsung-Yen Tsou, Chieh Chu, Yuan-Sun Natl Cheng Kung Univ Dept Elect Engn 1 Univ Rd Tainan Taiwan Natl Chung Cheng Univ Dept Elect Engn 168 Univ Rd Min Hsiung Chia Yi Taiwan

This study presents a low-power energy-harvesting circuit with error-correction demodulation for body sensor networks with radio-frequency identification (RFID) systems. The proposed circuit adopts a new structure that facilitates the demodulation of amplitude-shift-keying (ASK) signals, and it includes a power unit consisting of a wake-up circuit and a power-on-reset control circuit. The wireless bio-signal acquisition system and the digital processor are implemented on a field-programmable gate array to demonstrate the proposed RFID tag. The proposed energy-harvesting circuit can substantially decrease the capacitance used by the demodulator circuit and the wake-up circuit to as low as 14 pF. Moreover, a detection circuit and a correcting circuit are utilised to reduce the bit error rate of decoding. The wireless bio-signal acquisition scenario is also set up and the communication signal between reader and tag is measured to demonstrate the system that can be employed in body sensor network with the healthcare system. The chip was implemented in complementary metal-oxide-semiconductor 0.18 mu m technology. The sensitivity of this work is - 13 dBm. The pulse width error can be reduced to <1% by the error-correction demodulator to fit the EPC Gen-2 standard.

关键词： radiofrequency identification biomedical electronics energy harvesting error correction codes amplitude shift keying demodulators body sensor networks health care low-power electronics detector circuits CMOS integrated circuits field programmable gate arrays wireless energy-harvesting circuit wireless energy-harvesting system error-correction ASK demodulator body sensor network ultra-high-frequency RFID healthcare system radio-frequency identification system amplitude-shift-keying signal demodulation power unit wake-up circuit power-on-reset control circuit low-power energy-harvesting circuit wireless bio-signal acquisition system digital processor field-programmable gate array RFID tag detection circuit correcting circuit bit error rate decoding communication signal complementary metal-oxide-semiconductor technology pulse width error EPC Gen-2 standard size 0 18 mum

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Optimizing CNN-Based Hyperspectral Image Classification on FPGAs 15th

Optimizing CNN-Based Hyperspectral Image Classification on F...

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15th International Symposium on Applied Reconfigurable Computing

作者： Liu, Shuanglong Chu, Ringo S. W. Wang, Xiwei Luk, Wayne Imperial Coll London Dept Comp London England UCL Dept Comp Sci London England China Acad Space Technol Beijing Peoples R China

ISBN: (纸本)9783030172268;9783030172275

Hyperspectral image (HSI) classification has been widely adopted in remote sensing imagery analysis applications which require high classification accuracy and real-time processing speed. Convolutional neural networks (CNNs)-based methods have been proven to achieve state-of-the-art accuracy in classifying HSIs. However, CNN models are often too computationally intensive to achieve real-time response due to the high dimensional nature of HSI, compared to traditional methods such as Support Vector Machines (SVMs). Besides, previous CNN models used in HSI are not specially designed for efficient implementation on embedded devices such as FPGAs. This paper proposes a novel CNN-based algorithm for HSI classification which takes into account hardware efficiency and thus is more hardware friendly compared to prior CNN models. An optimized and customized architecture which maps the proposed algorithm on FPGA is then proposed to support real-time on-board classification with low power consumption. Implementation results show that our proposed accelerator on a Xilinx Zynq 706 FPGA board achieves more than 70x faster than an Intel 8-core Xeon CPU and 3x faster than an NVIDIA GeForce 1080 GPU. Compared to previous SVM-based FPGA accelerators, we achieve comparable processing speed but provide a much higher classification accuracy.

关键词： Hyperspectral image classification Deep learning Convolution neural network field-programmable gate array

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Real-Time Variation Mapping for parametric defect localization on ICs. Proof of concept, improvements, and application to new parameters

Real-Time Variation Mapping for parametric defect localizati...

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IEEE International Reliability Physics Symposium (IRPS)

作者： Saury, L. Cany, S. ST Ericsson Failure Anal Lab F-38019 Grenoble France

ISBN: (纸本)9781457716799

Localization of parametric defects on Analog / Mixed Signal and RF devices remains a challenge today. A very promising dynamic technique to address this issue is the parametric Variation Mapping (xVM) under Thermal Laser Stimulation (TLS). In this paper, we stress the importance of high-speed integrated solution for an efficient xVM implementation, which leads to the concept of Real-Time Variation Mapping (RTVM). Two concrete FPGA-based RTVM solutions are described and validated on Analog and RF case studies. Detailed results are presented and new developments are introduced.

关键词： real-time variation mapping field-programmable gate array fault isolation parametric defects

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Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA 29

Hybrid Dot-Product Calculation for Convolutional Neural Netw...

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29th International Conference on field-programmable Logic and Applications (FPL)

作者： Vestias, Mario Duarte, Rui Policarpo de Sousa, Jose T. Neto, Horacio Inst Politecn Lisboa INESC ID ISEL Lisbon Portugal Univ Lisbon INESC ID Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9781728148847

Convolutional Neural Networks (CNN) are quite useful in edge devices for security, surveillance, and many others. Running CNNs in embedded devices is a design challenge since these models require high computing power and large memory storage. Data quantization is an optimization technique applied to CNN to reduce the computing and memory requirements. The method reduces the number of bits used to represent weights and activations, which consequently reduces the size of operands and of the memory. The method is more effective if hybrid quantization is considered in which data in different layers may have different bit widths. This article proposes a new hardware module to calculate dot-products of CNNs with hybrid quantization. The module improves the implementation of CNNs in low density FPGAs, where the same module runs dot-products of different layers with different data quantizations. We show implementation results in ZYNQ7020 and compare with state-of-the-art works. Improvements in area and performance are achieved with the new proposed module.

关键词： Deep learning Convolutional Neural Network Embedded computing Hybrid quantization field-programmable gate array

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Challenges Designing for FPGAs Using High-Level Synthesis

Challenges Designing for FPGAs Using High-Level Synthesis

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IEEE High Performance Extreme Computing Virtual Conference (HPEC)

作者： Faber, Clayton J. Harris, Steven D. Xiao, Zhili Chamberlain, Roger D. Cabrera, Anthony M. Washington Univ St Louis McKelvey Sch Engn St Louis MO USA Oak Ridge Natl Lab Architectures & Performance Grp Oak Ridge TN USA

ISBN: (数字)9781665497862

ISBN: (纸本)9781665497862

High-Level Synthesis (HLS) tools are aimed at enabling performant FPGA designs that are authored in a high-level language. While commercial HLS tools are available today, there is still a substantial performance gap between most designs developed via HLS relative to traditional, labor intensive approaches. We report on several cases where an anticipated performance improvement was either not realized or resulted in decreased performance. These include: programming paradigm choices between data parallel vs. pipelined designs;dataflow implementations;configuration parameter choices;and handling odd data set sizes. The results point to a number of improvements that are needed for HLS tool flows, including a strong need for performance modeling that can reliably guide the compilation optimization process.

关键词： HLS FPGA High-Level Synthesis field-programmable gate array

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An All Digital Speed Adaptive Maximum Power Point Tracker for Automotive Photovoltaic Applications 3

An All Digital Speed Adaptive Maximum Power Point Tracker fo...

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3rd International Conference on Renewable Energy Research and Application (ICRERA)

作者： Strache, Sebastian Wunderlich, Ralf Heinen, Stefan Rhein Westfal TH Aachen Integrated Analog Circuits & RF Syst Lab Aachen Germany

ISBN: (纸本)9781479937950

This paper proposes an all digital speed and step size adaptive maximum power point tracker (MPPT) for photovoltaic (PV) power generation, supporting the power supply of vehicles. To harvest significant amounts of energy in this application the MPPT has to deal with fast changing irradiance and severe shading. It has to achieve high tracking speed while maintaining tracking errors below 1 %. The presented modified perturb and observe (P&O) MPPT algorithm meets these requirements by applying digital filtering to detect the settling of the input voltage automatically. This enables minimal sampling time for each situation and, hence, very fast convergence to the maximum power point (MPP). The developed algorithm has been implemented on a field-programmable gate array (FPGA) and verified with an experimental setup. It achieves about 9 kHz average switching frequency while maintaining a tracking accuracy above 99.8 %.

关键词： automotive electrics convergence digital filters field programmable gate arrays maximum power point trackers perturbation techniques solar powered vehicles FPGA P and O MPPT algorithm PV power generation all digital speed adaptive maximum power point tracker automotive photovoltaic application digital filtering field-programmable gate array irradiance perturb and observe MPPT algorithm sampling time switching frequency tracking error vehicle power supply Accuracy Convergence Current measurement field programmable gate arrays Maximum power point trackers Time-frequency analysis Voltage measurement

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