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检索条件"主题词=Field-programmable gate array"

共 570 条记录，以下是341-350 订阅

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Setting the PACE in IRSP: A reconfigurable PC-based array control electronics system for infrared scene projection

Setting the PACE in IRSP: A reconfigurable PC-based array co...

引用

Conference on Technologies for Synthetic Environments - Hardware-in-the-Loop Testing VIII

作者： Goldsmith, GC Herald, WL Erickson, RA Irvine, WS Mackin, PR Bryant, P Lindberg, B USAF Res Lab Munit Directorate Eglin AFB FL 32542 USA

ISBN: (纸本)0819449520

The development of a new generation PC-based array control electronics (PACE) system was completed during the first quarter of 2003 in the Kinetic Kill Vehicle Hardware-in-the-loop (KHILS) facility. This system replaces the bulky VME-based system that was the previous standard with more compact digital control electronics using field-programmable gate array (FPGA) technology hosted on a personal computer. The analog interface electronics (AIE) were redesigned to eliminate obsolete components and miniaturize the package for better compatibility with harsh environments. The resulting PACE system supports both Santa Barbara Infrared Inc. (SBIR) and Honeywell Technology Center's (HTC's) 512 x 512 legacy emitter array infrared projection devices as well as SBIR's upcoming 1024 x 1024 and next-generation 512 x 512 arrays. Two FPGA-based PCI boards enable this system to reconfigure the inputs, processing and outputs of the projection electronics through firmware loaded from the control PC. The increased flexibility provides potential for additional real-time functions such as distortion correction, convolution and calibration to be implemented along with nonuniformity correction (NLJC) techniques by simply reconfiguring firmware. This paper describes the capabilities of the new PACE system in terms of current and future hardware-in-the-loop (HITL) requirements.

关键词： infrared projector emitter arrays field-programmable gate array real-time processing nonuniformity correction

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An Instrumentation System for an Embedded Linux-Based Flight Controller

An Instrumentation System for an Embedded Linux-Based Flight...

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65th IEEE Autotestcon Conference (IEEE AUTOTESTCON)

作者： Don, Michael Schomer, Nathan Grabner, Mitchell Miller, Cory Hallameyer, Jonathan DEVCOM Army Res Lab Weap & Mat Res Directorate Aberdeen Proving Ground MD 21005 USA SURVICE Engn Co 4695 Millennium Dr Belcamp MD USA

ISBN: (纸本)9781728154008

The DEVCOM Army Research Laboratory has redesigned its Multi-functional Instrumentation and Data Acquisition System (MIDAS) to support an embedded Linux-based flight controller for its smart munitions research. This includes field-programmable gate array development of a serial peripheral interface between the sensor board and flight controller, integration of three new digital sensors using a soft-core processor, and the design of a custom Linux software stack. This new version of MIDAS has been successfully used in several flight experiments, and will continue to support future smart munitions research and development.

关键词： instrumentation data acquisition embedded software field-programmable gate array flight control

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Architecture Exploration for HLS-Oriented FPGA Debug Overlays 18

Architecture Exploration for HLS-Oriented FPGA Debug Overlay...

引用

ACM/SIGDA International Symposium on field-programmable gate arrays (FPGA)

作者： Jamal, Al-Shahna Goeders, Jeffrey Wilton, Steven J. E. Univ British Columbia Vancouver BC Canada Brigham Young Univ Provo UT 84602 USA

ISBN: (纸本)9781450356145

High-Level Synthesis (HLS) promises improved designer productivity, but requires a debug ecosystem that allows designers to debug in the context of the original source code. Recent work has presented in-system debug frameworks where instrumentation added to the design collects trace data as the circuit runs, and a software tool that allows the user to replay the execution using the captured data. When searching for the root cause of a bug, the designer may need to modify the instrumentation to collect data from a new part of the design, requiring a lengthy recompile. In this paper, we propose a flexible debug overlay family that provides software-like debug turn-around times for HLS generated circuits. At compile time, the overlay is added to the design and compiled. At debug time, the overlay can be configured many times to implement specific debug scenarios without a recompilation. This paper first outlines a number of "capabilities" that such an overlay should have, and then describes architectural support for each of these capabilities. The cheapest overlay variant allows selective variable tracing with only a 1.7% increase in area overhead from the baseline debug instrumentation, while the deluxe variant offers 2x-7x improvement in trace buffer memory utilization with conditional buffer freeze support.

关键词： field-programmable gate array Debugging High-Level Synthesis

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Power Electronics Control with System-on-a-Chip-Based Platforms 20

Power Electronics Control with System-on-a-Chip-Based Platfo...

引用

IEEE 20th International Power Electronics and Motion Control Conference (PEMC)

作者： Guerreiro, Marco Kharade, Shrikant dos Santos, Pedro Liu, Steven Tech Univ Kaiserslautern Chair Control Syst Kaiserslautern Germany

ISBN: (数字)9781665496810

ISBN: (纸本)9781665496810

An emerging trend in power electronics control is the use of controllers based on a system-on-a-chip (SoC). SoCs provide a high-performance computing platform by embedding one or multiple processors and a field-programmable gate array (FPGA) on the same chip. This paper reviews SoCs for power electronics control applications, discussing aspects such as task allocations and available hardware and software tools. A design and experimental results of an SoC-based controller are discussed, and some of the SoC-based platforms built by researchers in power electronics control are reviewed.

关键词： power electronics embedded control system-on-a-chip field-programmable gate array

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OpenCL Performance on the Intel Heterogeneous Architecture Research Platform

OpenCL Performance on the Intel Heterogeneous Architecture R...

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IEEE High Performance Extreme Computing Conference (HPEC)

作者： Harris, Steven Chamberlain, Roger D. Gill, Christopher Washington Univ McKelvey Sch Engn St Louis MO 63110 USA

ISBN: (纸本)9781728192192

The fundamental operation of matrix multiplication is ubiquitous across a myriad of disciplines. Yet, the identification of new optimizations for matrix multiplication remains relevant for emerging hardware architectures and heterogeneous systems. Frameworks such as OpenCL enable computation orchestration on existing systems, and its availability using the Intel High Level Synthesis compiler allows users to architect new designs for reconfigurable hardware using C/C++. Using the HARPv2 as a vehicle for exploration, we investigate the utility of several traditional matrix multiplication optimizations to better understand the performance portability of OpenCL and the implications for such optimizations on cache coherent heterogeneous architectures. Our results give targeted insights into the applicability of best practices that were designed for existing architectures when used on emerging heterogeneous systems.

关键词： Design space search HARP High-level synthesis SGEMM field-programmable gate array

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Clock and carrier recovery in high-speed coherent optical communication systems 2

Clock and carrier recovery in high-speed coherent optical co...

引用

2nd International Conference on Applications of Optics and Photonics

作者： Amado, Sofia B. Ferreira, Ricardo Costa, Pedro S. Guiomar, Fernando P. Ziaie, Somayeh Teixeira, Antonio L. Muga, Nelson J. Pinto, Armando N. Univ Aveiro Dept Elect Telecommun & Informat Aveiro Portugal Inst Telecomun P-3810193 Aveiro Portugal Portugal Telecom PT Desenvolvimento Sistemas Rede Inovac Sistemas Aveiro Portugal

ISBN: (纸本)9781628413618

In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 field-programmable gate array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).

关键词： Coherent detection digital signal processing analog-to-digital converters field-programmable gate array clock recovery carrier-recovery real-time

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Alternatives in FPGA-based SAD implementations 1

Alternatives in FPGA-based SAD implementations

引用

IEEE International Conference on field-programmable Technology (FPT)

作者： Wong, S Stougie, B Cotofana, S Delft Univ Technol Comp Engn Lab Delft Netherlands

ISBN: (纸本)0780375742

In multimedia processing, it is well-known that the sum-of-absolute-differences (SAD) operation is the most time-consuming operation when implemented in software running on programmable processor cores. This is mainly due to the sequential characteristic of such an implementation. In this paper, we investigate several hardware implementations of the SAD operation and map the most promising one in FPGA. Our investigation shows that an adder tree based approach yields the best results in terms of speed and area requirements and has been implemented as such by writing high-level VHDL code. The design was functionally verified by utilizing the MAX+plus II 10.1 Baseline software package from Altera Corp. and then synthesized by utilizing the LeonardoSpectrum software package from Exemplar Logic Inc. Preliminary results show that the design can be clocked at 380 Mhz. This result translates into a faster than real-time full search in motion estimation for the main profile/main level of the MPEG-2 standard.

关键词： sum of absolute difference field-programmable gate array hardware synthesis

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HLScope: High-Level Performance Debugging for FPGA Designs 25

HLScope: High-Level Performance Debugging for FPGA Designs

引用

25th IEEE Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Choi, Young-Kyu Cong, Jason Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781538640371

In their quest for further optimization, field-programmable gate array (FPGA) designers often spend considerable time trying to identify the performance bottleneck in a current design. But since FPGAs do not have built-in high-level probes for performance analysis, manual effort is required to insert custom hardware monitors. This, however, is a time-consuming process which calls for automation. Previous work automates the process of inserting hardware monitors into the communication channels or the finite-state machine, but the instrumentation is applied in low-level hardware description languages (HDL) which limits the comprehensibility in identifying the root cause of stalls. Instead, we propose a performance debugging methodology based on high-level synthesis (HLS). High-level analysis allows tracing the cause of stalls on a function or loop level, which provides a more intuitive feedback that can be used to pinpoint the performance bottleneck. In this paper we propose HLScope, a source-to-source transformation framework based on Vivado HLS for automated performance analysis. We present a method for analyzing the information collected from the software simulation to estimate the stall rate and its cause without the need for FPGA bitstream generation. For detailed analysis, an in-FPGA analysis method is proposed that can be natively integrated into the HLS environment. Experiments show that the parameter extraction from the simulation process is orders of magnitude faster than bitstream generation, with a 2.2% cycle difference on average. In-FPGA flow consumes only about 170 LUTs and a BRAM per monitored module and provides cycle-accurate results.

关键词： field-programmable gate array High-level synthesis Performance debugging Source-to-source transformation

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Video Broadcast via a Lamp

Video Broadcast via a Lamp

引用

12th International Conference on Transparent Optical Networks (ICTON)

作者： Vucic, Jelena Kottke, Christoph Fernandez, Luz Nerreter, Stefan Walewski, Joachim Habel, Kai Langer, Klaus-Dieter Fraunhofer Inst Telecommun Heinrich Hertz Inst Einsteinufer 37 D-10587 Berlin Germany Siemens AG Corp Technol D-13629 Berlin Germany Siemens AG Corp Technol Commun Technol D-81739 Munich Germany

We report the implementation of a real-time visible-light link, based on discrete multitone modulation of a high-brightness LED. Parallel transmission of three high-definition video streams was also demonstrated.

ISBN: (纸本)9781424477982

关键词： Visible light communications white light-emitting diode discrete multitone field-programmable gate array

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Automated Multi-Device Placement, I/O Voltage Supply Assignment, and Pin Assignment in Circuit Board Design

Automated Multi-Device Placement, I/O Voltage Supply Assignm...

引用

12th International Conference on field-programmable Technology (FPT)

作者： Seemuth, Daniel P. Morrow, Katherine Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781479921980;9781479921997

Embedded systems often contain many components, some with multiple field programmable gate arrays (FPGAs). Designing Printed Circuit Boards (PCBs) for these systems can be a complex process that is often tedious, error-prone, and time-intensive. Existing computer-aided design tools require designers to manually insert components and explicitly define the connections between every component on the PCB-a cumbersome process. A fast PCB design framework requiring reduced designer time and effort would be particularly advantageous for rapid prototyping and short production run PCBs. Therefore, this paper proposes a novel, freely-available open-source framework to capture design intent and automatically implement the design details. Designers express connectivity at a higher level of abstraction than enumerating or drawing each individual trace between components. Given the components and connection requirements, the proposed framework automatically generates component placements, I/O voltage supply assignments, and FPGA pin assignments to minimize trace length. We also propose a novel method to improve trace length estimations during placement, before FPGA pins have actually been assigned to those connections. The proposed framework quickly explores large solution spaces, enabling rapid prototyping and design space exploration, and can lead to lower costs in design time and other non-recurring expenses. We demonstrate that it produces favorable results for various design requirements, which suggests the framework will be especially appreciated by designers of systems with multiple FPGAs having large numbers of flexible pins.

关键词： printed circuit board design capture pin assignment field-programmable gate array high-level specification computer-aided design electronic design automation rapid prototyping

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