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检索条件"主题词=Field-programmable gate array"

共 571 条记录，以下是351-360 订阅

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Automated Multi-Device Placement, I/O Voltage Supply Assignment, and Pin Assignment in Circuit Board Design

Automated Multi-Device Placement, I/O Voltage Supply Assignm...

引用

12th International Conference on field-programmable Technology (FPT)

作者： Seemuth, Daniel P. Morrow, Katherine Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781479921980;9781479921997

Embedded systems often contain many components, some with multiple field programmable gate arrays (FPGAs). Designing Printed Circuit Boards (PCBs) for these systems can be a complex process that is often tedious, error-prone, and time-intensive. Existing computer-aided design tools require designers to manually insert components and explicitly define the connections between every component on the PCB-a cumbersome process. A fast PCB design framework requiring reduced designer time and effort would be particularly advantageous for rapid prototyping and short production run PCBs. Therefore, this paper proposes a novel, freely-available open-source framework to capture design intent and automatically implement the design details. Designers express connectivity at a higher level of abstraction than enumerating or drawing each individual trace between components. Given the components and connection requirements, the proposed framework automatically generates component placements, I/O voltage supply assignments, and FPGA pin assignments to minimize trace length. We also propose a novel method to improve trace length estimations during placement, before FPGA pins have actually been assigned to those connections. The proposed framework quickly explores large solution spaces, enabling rapid prototyping and design space exploration, and can lead to lower costs in design time and other non-recurring expenses. We demonstrate that it produces favorable results for various design requirements, which suggests the framework will be especially appreciated by designers of systems with multiple FPGAs having large numbers of flexible pins.

关键词： printed circuit board design capture pin assignment field-programmable gate array high-level specification computer-aided design electronic design automation rapid prototyping

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AQSS: Accelerator of quantization neural networks with stochastic approach 6

AQSS: Accelerator of quantization neural networks with stoch...

引用

6th International Symposium on Computing and Networking (CANDAR) - Across Practical Development and Theoretical Research

作者： Ueki, Takeo Iwai, Keisuke Matsubara, Takashi Kurokawa, Takakazu Natl Def Acad Japan Dept Comp Sci Hashirimizu 1-10-20 Yokosuka Kanagawa 2390811 Japan

ISBN: (纸本)9781538691847

In recent years, Deep Neural Network (DNN) s have become widely spread. Several high-throughput hardware implementations for DNNs have been proposed. One of the key points for hardware implementations of DNNs is to reduce their power consumption because DNNs require a lot of product-sum operations. Previous papers presented some accelerators using logarithmic quantization to reduce the power consumption by replacing multipliers with shifters. However, most of them are implemented only for inference. In this paper, an Accelerator of Quantization neural networkS with Stochastic approach (AQSS) is proposed. It uses a stochastic approach for logarithmic quantization, and enables DNNs to infer or to learn using logarithmic quantization. A prototype of AQSS is implemented on a field-programmable gate array (FPGA) (Intel Arria 10 GX 1150) and synthesized with Intel Quartus Prime 17.1 Standard Edition. As a result, it is confirmed to have 1.8 times the power efficiency of GPU.

关键词： neural networks deep learning field-programmable gate array hardware logarithmic quantization

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Application of FPGA based PLL in a CSI fed induction heating prototype

Application of FPGA based PLL in a CSI fed induction heating...

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IEEE International Conference on Power Electronics, Drives, and Energy Systems (PEDES)

作者： Roy, Molay Sengupta, Mainak Indian Inst Engn Sci & Technol Dept Elect Engn Howrah 711103 WB India

ISBN: (纸本)9781479963737

Modern induction heating (IH) power converters operate marginally above resonant frequency to supply power to the targeted work-piece at near unity power factor (upf). The resonant frequency continuously increases as the work-piece gets heated up. A possible method of dynamically detecting the resonant frequency may be to calculate the phase-shift between current and voltage continuously during the process. The phase-shift between voltage and current is ideally zero at resonance. So resonant frequency may be identified by varying the frequency until the phase-shift is zero. For this some controllers use a phase-locked loop (PLL) strategy. In this paper, the dynamic tracking of resonant frequency, using a field-programmable gate array (FPGA) based digital-PLL, is presented. The scheme is first simulated off-line. Finally, the logic is implemented on controller hardware and practically tested in a laboratory made experimental set-up of 2kW at around 10kHz.

关键词： field programmable gate arrays induction heating invertors phase locked loops CSI fed induction heating prototype FPGA IH power converters PLL dynamic tracking field-programmable gate array induction heating power converters phase-locked loop resonant frequency Coils Electromagnetic heating field programmable gate arrays Frequency conversion Phase locked loops Prototypes Resonant frequency Phase locked loops field programmable gate arrays resonant frequencies Prolymphocytic Leukemia dynamic tracking Induction heating Electromagnetic heating Inventors Frequency conversion Coils Phase shift PROTOTYPE unity power factor

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An-FPGA based classification system by using a neural network and an improved particle swarm optimization algorithm 8

An-FPGA based classification system by using a neural networ...

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Joint 8th International Conference on Soft Computing and Intelligent Systems (SCIS) / 17th International Symposium on Advanced Intelligent Systems (ISIS)

作者： Dang, Tuan Linh Hoshino, Yukinobu Kochi Univ Technol Sch Syst Engn Kochi Japan

ISBN: (纸本)9781509026784

This paper presents a development of a soft intelligent system on chip. This system is used to solve the classification problem. In this system, a neural network is trained by the particle swarm optimization (PSO) algorithm. This algorithm is hardware implemented on a real device. An improved version of the standard PSO algorithm called the PSOseed algorithm is also introduced in this paper in order to reduce the possibility when the standard PSO gets stuck in the local minimum. The experimental results show that the neural network trained by the particle swarm optimization algorithm was successful hardware implemented. In addition, the PSOseed algorithm also obtained a better performance than the standard PSO algorithm in our experiments.

关键词： field-programmable gate array neural network particle swarm optimization soft intelligent systems on chip velocity control

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VLSI Architecture of a High-Performance Neural Spiking Activity Simulator Based on Generalized Volterra Kernel 14

VLSI Architecture of a High-Performance Neural Spiking Activ...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Li, Will X. Y. Xin, Yao Song, Dong Berger, Theodore W. Cheung, Ray C. C. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ So Calif Ctr Neural Engn Dept Biomed Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781479948338

It is well known that information is represented and transmitted among neuronal units by a series of all-or-none "neural codes". In neuroinformatics study, this coding process, also termed as "spiking activity", is not straightforward for prediction. It is owing to the high nonlinearity and dynamic property involved in generation of the neuronal spikes. In this paper, a novel generalized Volterra kernel-based neural spiking activity simulator is introduced for prediction of the neural codes in mammalian hippocampal region. High-performance VLSI architecture is established for the simulator based on high-order Volterra kernels involving cross terms. The effectiveness and efficiency of the simulator are proven in experimental settings. This simulator has the potential to serve as a core functional unit in future hippocampal cognitive neural prosthesis.

关键词： neural spiking activity neural simulator field-programmable gate array neural prosthesis

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An FPGA-based Implementation Method for Quadratic Spiking Neuron Model 11

An FPGA-based Implementation Method for Quadratic Spiking Ne...

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11th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Lin, Xianghong Lu, Han Pi, Xiaomei Wang, Xiangwen Northwest Normal Univ Coll Comp Sci & Engn Lanzhou 730070 Peoples R China

ISBN: (纸本)9781728196565

In the innovative neural prostheses, the biological cell assemblies of the biological nervous system can be replaced by artificial organs, which makes the idea of dynamically interface biological neurons even more urgent. To mimic and investigate the activity of biological neural networks, many different architectures and technologies in the field of neuromorphic have been developed at present. When structuring simple neuron models, researchers use field programmable gate arrays (FPGAs) to obtain better accuracy and real-time performance. This paper uses FPGAs to achieve the circuit design of the neuron model, such that based on the biologically plausible the quadratic spiking neuron model, can simulate the neuron spiking behaviors of thalamus neurons and hippocampal CA1 pyramidal neurons. After the FPGA hardware architecture of the neuron model is designed and implemented, this model can better simulate the spiking behaviors observed in biological neurons.

关键词： quadratic spiking neuron model Neuromorphic field-programmable gate array hardware implementation

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Accelerated Large-Scale Multiple Sequence Alignment with Reconfigurable Computing

Accelerated Large-Scale Multiple Sequence Alignment with Rec...

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作者： Lloyd, G. Scott Brigham Young University

学位级别：Ph.D.

Multiple Sequence Alignment (MSA) is a fundamental analysis method used in bioinformatics and many comparative genomic applications. The time to compute an optimal MSA grows exponentially with respect to the number of sequences. Consequently, producing timely results on large problems requires more efficient algorithms and the use of parallel computing resources. Reconfigurable computing hardware provides one approach to the acceleration of biological sequence alignment. Other acceleration methods typically encounter scaling problems that arise from the overhead of inter-process communication and from the lack of parallelism. Reconfigurable computing allows a greater scale of parallelism with many custom processing elements that have a low-overhead interconnect. The proposed parallel algorithms and architecture accelerate the most computationally demanding portions of MSA. An overall speedup of up to 150 has been demonstrated on a large data set when compared to a single processor. The reduced runtime for MSA allows researchers to solve the larger problems that confront biologists today.

关键词： communication network communication protocol computer architecture interface modules dynamic programming field-programmable gate array FPGA sequence alignment reconfigurable hardware traceback

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Systolic Architectures for Efficient Deep Neural Network Implementations with Assured Performance

Systolic Architectures for Efficient Deep Neural Network Imp...

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作者： Zhang, Sai Qian Harvard University

学位级别：Ph.D.

Deep neural networks (DNNs) have gained major interests in a variety of application domains including computer vision, natural language processing, autonomous driving, etc. While DNNs deliver state-of-the-art accuracies on many AI tasks, they comes at the cost of high computational complexity. Accordingly, designing efficient hardware architectures for DNNs is an important step towards enabling the wide deployment of DNNs in the modern AI system. Although DNNs have been developed to solve a variety of problems, the major arithmetic operations involved in these DNNs are almost identical: a series of matrix multiplications between the inputs and the DNN weights. Therefore, an efficient hardware architecture for supporting matrix operations plays a key role in DNN implementations. Systolic arrays are widely known to be appealing for matrix multiplication operation due to their regular layout of processing elements, efficient interprocessor communication, and reduced memory access. This has led to numerous commercial DNN accelerators using systolic arrays for matrix multiplication (e.g., Google Tensor Processing Unit). In this thesis, we explore innovative systolic architectures that support DNN executions at low cost. We leverage the recent advances in DNN pruning (removing superfluous parameters from DNNs) and DNN quantization (converting the high-precision DNN parameters into low-precision parameters), and describe (1) techniques to overcome the limitation of systolic arrays in addressing sparse matrices of irregular sparsity structures and in addressing load balancing over systolic cells, and (2) new uses of systolic arrays in DNNs. By evaluating the novel systolic architectures with both Application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA), we demonstrate the superior performance of our systolic designs in terms of both processing latency and energy efficiency across multiple DNN models and datasets. In addition to the evaluation

关键词： Deep neural networks Application-specific integrated circuit field-programmable gate array

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Fast beam steering and agile wavefront control with an optical phased array

Fast beam steering and agile wavefront control with an optic...

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AOS Australian Conference on Optical Fibre Technology (ACOFT) / Australian Conference on Optics, Lasers, and Spectroscopy (ACOLS)

作者： Gozzard, David R. Spollard, James T. Roberts, Lyle E. Sibley, Paul G. McClelland, David E. Shaddock, Daniel A. Australian Natl Univ Res Sch Phys & Engn Canberra ACT Australia

ISBN: (纸本)9781510631410

Optical phased arrays (OPAs) are a solid-state device able to manipulate the distribution of optical power without the use of mechanical beam steering systems and have potential applications in free-space laser communications, target acquisition and tracking, and interferometry. Here we present a scalable OPA and digital control architecture capable of steering a laser beam at MHz frequencies, and having arbitrary control over the beam wavefront.

关键词： optical phased array field-programmable gate array fats steering wavefront control phase sensing

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Design and Implementation of Nonlinear Junction Detection FPGA-based System

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International Conference on Mechatronics and Materials Processing (ICMMP 2011)

作者： Zhang, Jie Liu, Xiao Jie Li, Yue Jilin Univ Coll Commun Engn Changchun 130012 Peoples R China Jilin Univ Editorial Dept Journal Changchun 130012 Peoples R China Jiangsu Teachers Univ Technol Sch Elect Engn & Informat Changzhou 213001 Peoples R China

ISBN: (纸本)9783037852385

In this work, according to the nonlinear re-radiation characteristic of semiconductor PN junction, the nonlinear junction detection system for semiconductor junction targets based on second harmonic reception is designed on the basis of the analysis for nonlinear re-radiation characteristics of semiconductor junction targets, derivation of the system implementation scheme. By the system simulation and experiment, the preliminary test results show that the system can detect well the junction of nonlinear component with gain high enough for signal detection.

关键词： Nonlinear junction Detection system field-programmable gate array

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