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International Workshop on Advanced Imaging Technology (IWAIT)

作者： Nagamine, Yuya Yoshihiro, Kazuki Shibata, Masatoshi Yamada, Hideo Enokida, Shuichi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Fukuoka Japan EQUOS Res Co Ltd Tokyo Japan Kyushu Inst Technol Grad Sch Comp Sci & Syst Engn Fukuoka Japan

ISBN: (数字)9781510643659

ISBN: (纸本)9781510643659

In this study, we propose a hardware-oriented Gaussian mixture model - multiresolution co-occurrence histograms of oriented gradients (GMM-MRCoHOG) algorithm for efficient human detection by a field-programmable gate array (FPGA). GMM- MRCoHOG is a HOG-based human detection method in which the computation of angles is quantized to 36 directions and 2D Gaussian distribution computation causes a decrease in processing speed and an increase in hardware resource usage. We propose a hardware-oriented algorithm to solve these problems. First, we propose a rough angle computation method of comparison with a tangent table. Second, we propose a bit-shifting-based Gaussian distribution computation method. Experimental results show that the proposed hardware-oriented algorithm does not significantly reduce the detection accuracy of GMM-MRCoHOG. High-level synthesis results of the FPGA implementation show that fast, low-resource processing is possible.

关键词： Image processing Human detection Histograms of oriented gradients Gaussian mixture model Hardware-oriented algorithm field-programmable gate array

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Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs 28

Lite-CNN: A High-Performance Architecture to Execute CNNs in...

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28th International Conference on field programmable Logic and Applications (FPL)

作者： Vestias, Mario Duarte, Rui Policarpo de Sousa, Jose T. Neto, Horacio Inst Politecn Lisboa INESC ID ISEL Lisbon Portugal Univ Lisbon Inst Super Tecn INESC ID Lisbon Portugal

ISBN: (纸本)9781538685174

Due to the computational complexity of Convolutional Neural Networks (CNNs), high performance platforms are generally considered for their execution. However, CNNs are very useful in embedded systems and its execution right next to the source of data has many advantages, like avoiding the need for data communication. In this paper, we propose an architecture for CNN inference (Lite-CNN) that can achieve high performance in low density FPGAs. Lite-CNN adopts a fixed-point representation for both neurons and weights, which was already shown to be sufficient for most CNNs. Also, with a simple and known dot product reorganization, the number of multiplications is reduced to half. We show implementation results for 8 bit fixed-point in a ZYNQ7020 and extrapolate for other larger FPGAs. Lite-CNN achieves 410 GOPs in a ZYNQ7020.

关键词： Embedded computing Deep learning Convolutional Neural Network field-programmable gate array

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A Robust Approach to the Generation of High Quality Random Numbers 2

A Robust Approach to the Generation of High Quality Random N...

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Conference on Quantum Information Science and Technology II

作者： Bisadi, Zahra Fontana, Giorgio Moser, Enrico Pucker, Georg Pavesi, Lorenzo Univ Trento Dept Phys Nanosci Lab Via Sommarive 14 I-38123 Povo Trento Italy Bruno Kessler Fdn Ctr Mat & Microsyst Via Sommarive 18 I-38123 Povo Trento Italy

ISBN: (数字)9781510603974

ISBN: (纸本)9781510603967;9781510603974

A random number generation approach comprising a silicon nanocrystals LED (Si-NCs LED), silicon single photon avalanche photodiode (Si SPAD) and a field-programmable gate array (FPGA) is introduced. The Si-NCs LED is the source of entropy with photon emission in the visible range detectable by silicon detectors allowing the fabrication of an all-silicon-based device. The proposed quantum random number generator (QRNG) is robust against variations of the internal and external parameters such as aging of the components, changing temperature, the ambient interferences and the silicon detector artifacts. The raw data show high quality of randomness and passed all the statistical tests in National Institute of Standards and Technology (NIST) tests suite without the application of a post-processing algorithm. The efficiency of random number generation is 4-bits per detected photon.

关键词： Robust quantum random number generation silicon nanocrystals LED silicon single photon avalanche photodiode field-programmable gate array NIST tests suite

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Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices 1

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18th International Symposium on Applied Reconfigurable Computing

作者： Rognlien, Markus Que, Zhiqiang Coutinho, Jose G. F. Luk, Wayne Imperial Coll London Dept Comp 180 Queens Gate London England

ISBN: (数字)9783031199837

ISBN: (纸本)9783031199820;9783031199837

AI solutions, such as Deep Learning (DL), are becoming increasingly prevalent in edge devices. Many of these applications require low latency processing of large amounts of data within a tight power budget. In this context, reconfigurable embedded devices make a compelling option. Deploying DL models to reconfigurable devices does, however, present considerable challenges. One key issue is reconciling the often large compute requirements of DL models with the limited available resources on edge devices. In this paper, we present a hardware-aware optimization strategy for deploying DL neural networks to FPGAs, which automatically identifies hardware configurations that maximize resource utilization for a given level of computation throughput. We demonstrate our optimization approach on a sample neural network containing a combination of convolutional and fully connected layers, running on a sample FPGA target device, achieving a factor of 3.5 reduction in DSP block usage without affecting throughput when using performance mode. When using the compact mode, a factor of 7.4 reduction in DSP block usage is achieved, at the cost of 1.8 times decrease in throughput. Our approach works completely automatically without the need for human intervention or domain knowledge.

关键词： field-programmable gate array High-level synthesis Meta-programming Particle physics

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Traffic Flow Optimization using a Chaotic Boltzmann Machine Annealer on an FPGA 22

Traffic Flow Optimization using a Chaotic Boltzmann Machine ...

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22nd International Conference on field programmable Technology (ICFPT)

作者： Yoshioka, Kanta Tanaka, Yuichiro Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Kitakyushu Fukuoka Japan

ISBN: (纸本)9798350359114

We demonstrate a chaotic Boltzmann machine annealer, which is a field-programmable gate array (FPGA)-based high-performance annealing machine, and a control system powered by two open-source software packages. The annealer is employed in solving a large-scale real-world optimization problem, the traffic flow optimization. This involves distributing 500 car routes between the Haneda Airport area to the Pacifico Yokohama area, the venue of the International Conference on field programmable Technology 2023, while minimizing the total driving distance and preventing traffic jams. We obtain solutions that are comparable in accuracy to solutions of simulated annealing running on a graphics processing unit (GPU-SA) and a central processing unit (CPU-SA). The annealing machine on an FPGA is approximately 571 and 97600 times as fast as the GPUSA and the CPU-SA, respectively. We will demonstrate solving traffic flow optimization in the towns familiar to the visitors.

关键词： neural networks Ising machine annealing machine field-programmable gate array

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Velocity measurement by a vision sensor

Velocity measurement by a vision sensor

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IEEE International Conference on Computational Intelligence for Measurement Systems and Applications

作者： Malki, Suleyman Deepak, G. Mohanna, Vincent Ringhofer, Markus Spaanenburg, Lambert Lund Univ Dept Informat Technol S-22100 Lund Sweden

ISBN: (纸本)9781424402441

Vision sensors are of increasing interest for nonintrusive, remote measurements in industrial as well as consumer products. Their operation is based on intelligent techniques for image understanding, followed by robust quantification of the detected phenomenon. A well-known application area is movement detection and isolation. This paper discusses how movement can be detected and quantified by means of a single Cellular Neural Network, implemented as a Network-on-Chip and realized on a field-programmable gate-array. The final prototype can isolate a moving object and measure its velocity at a speed of 250 frames per second.

关键词： text recognition image understanding cellular neural network embedded system field-programmable gate array

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ME-TCAM: Memory-Efficient Ternary Content Addressable Memory Based on Multipumping-Enabled LUTRAM on FPGA

ME-TCAM: Memory-Efficient Ternary Content Addressable Memory...

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International Conference on Intelligent Computing and Human-Computer Interaction (ICHCI)

作者： Shi, Zilin Yang, Hui Liu, Rulin Yan, Jinli Qiao, Peng Wang, Baosheng Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China Natl Univ Def Technol Sci & Technol Parallel & Distributed Proc Lab PDL Changsha Peoples R China

ISBN: (纸本)9781665423168

Static random access memory (SRAM) on field programmable gate arrays (FPGAs) can be emulated to offer ternary content addressable memory (TCAM) functionality. However, SRAM-based TCAM wastes storage resources. This is due to the limited capacity of the physical addresses in the SRAM unit. This work proposes a LUTRAM-based TACM scheme on the FPGA called Memory-Efficient TCAM (ME-TCAM). ME-TCAM divides SRAM unit into multiple virtual blocks mapping to a portion of the TCAM table to store the more address information of the TCAM table. Operation on SRAM block means that increasing the overall emulated TCAM bits/SRAM. Moreover, ME-TCAM exploits Xilinx primitives to configure lookup tables (LUTs) as 32 x 2 lookup table RAMs (LUTRAMs). We implement ME-TCAM using LUTRAM with a size of 512 x 48 and 1024 x 144 on a Virtex-7 FPGA device. Compared with the state-of-the-art research DURE, ME-TCAM achieves at least 2.6 times more memory efficiency.

关键词： static random access memory ternary content addressable memory sram-based tcam field-programmable gate array multipumping technology

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FPGA based Multiprocessor Embedded System for Real-Time Image Processing 15

FPGA based Multiprocessor Embedded System for Real-Time Imag...

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15th International Conference on Control, Automation and Systems (ICCAS)

作者： Masud, Nauman Nasir, Jahanzeb Nazir, Muhammad Shahid Aqil, Muhammad Pakistan Inst Engn & Appl Sci Dept Elect Engn PO 45650 Islamabad Pakistan

ISBN: (纸本)9788993215090

In this paper, a field-programmable gate array (FPGA) based multiprocessor architecture is proposed for real-time image processing. The system is developed based on a hardware-software co-design philosophy. A total of five soft-core MicroBlaze processors are configured in master-slave topology and furnished with BRAM cores. A frame grabbing and a serial port cores are developed for camera and PC interfacing, respectively. Each processor can be configured to perform a certain task and all processors operate in parallel, hence providing high speed computing desirable for real -time image processing. The validity of the proposed embedded platform, realized on an XtremeDSP Development Kit-IV, is demonstrated by grabbing and processing real-time images.

关键词： Embedded system field-programmable gate array image processing real-time multicore processing

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Wireless energy-harvesting circuit and system with error-correction ASK demodulator for body sensor network with ultra-high-frequency RFID healthcare system

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IET WIRELESS SENSOR SYSTEMS 2018年第1期8卷 36-44页

作者： Lee, Shuenn-Yuh Chen, Tsung-Yen Tsou, Chieh Chu, Yuan-Sun Natl Cheng Kung Univ Dept Elect Engn 1 Univ Rd Tainan Taiwan Natl Chung Cheng Univ Dept Elect Engn 168 Univ Rd Min Hsiung Chia Yi Taiwan

This study presents a low-power energy-harvesting circuit with error-correction demodulation for body sensor networks with radio-frequency identification (RFID) systems. The proposed circuit adopts a new structure that facilitates the demodulation of amplitude-shift-keying (ASK) signals, and it includes a power unit consisting of a wake-up circuit and a power-on-reset control circuit. The wireless bio-signal acquisition system and the digital processor are implemented on a field-programmable gate array to demonstrate the proposed RFID tag. The proposed energy-harvesting circuit can substantially decrease the capacitance used by the demodulator circuit and the wake-up circuit to as low as 14 pF. Moreover, a detection circuit and a correcting circuit are utilised to reduce the bit error rate of decoding. The wireless bio-signal acquisition scenario is also set up and the communication signal between reader and tag is measured to demonstrate the system that can be employed in body sensor network with the healthcare system. The chip was implemented in complementary metal-oxide-semiconductor 0.18 mu m technology. The sensitivity of this work is - 13 dBm. The pulse width error can be reduced to <1% by the error-correction demodulator to fit the EPC Gen-2 standard.

关键词： radiofrequency identification biomedical electronics energy harvesting error correction codes amplitude shift keying demodulators body sensor networks health care low-power electronics detector circuits CMOS integrated circuits field programmable gate arrays wireless energy-harvesting circuit wireless energy-harvesting system error-correction ASK demodulator body sensor network ultra-high-frequency RFID healthcare system radio-frequency identification system amplitude-shift-keying signal demodulation power unit wake-up circuit power-on-reset control circuit low-power energy-harvesting circuit wireless bio-signal acquisition system digital processor field-programmable gate array RFID tag detection circuit correcting circuit bit error rate decoding communication signal complementary metal-oxide-semiconductor technology pulse width error EPC Gen-2 standard size 0 18 mum

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Analysis of the programmable Soft IP-cores Implementation for FPGAs

Analysis of the Programmable Soft IP-cores Implementation fo...

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Khvatov, Vasilii M. Zheleznikov, Daniil A. Gavrilov, Sergey, V Russian Acad Sci IPPMRAS Inst Design Problems Microelect Moscow Russia

ISBN: (纸本)9781665404761

Soft programmable IP-cores are usually used to speed up the integrated circuits design in FPGA. Soft blocks are formed from programmable logical FPGA elements independently from specific location on the FPGA and do not have pre-routed paths. Some FPGA architectures contain specialized resources to improve IP-cores design efficiency. It is necessary to consider these resources in CAD methods and components development. The paper presents the comparative analysis of two types of soft IP-cores implementation. The first type utilizes the architectural features of the FPGA due to a special block library. The second one obtains the results of automatic synthesis in a standard elements basis. The final size of designed IP-cores and the amount of utilized routing resources are compared. Also, the paper describes the specifics of the FPGA routing resources usage and the other implementation issues of such soft IP-cores as an n-bit adder / subtractor, an up-to-N counter, and a shift register.

关键词： IP-cores Computer Aided Design CAD field-programmable gate array FPGA Design Flow Routing

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