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检索条件"主题词=Field-programmable gate array"

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Design and implementation of Galaxian game based on FPGA Architecture

Design and implementation of Galaxian game based on FPGA Arc...

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2nd International Conference on Mechanical Design and Power Engineering (ICMDPE 2013)

作者： Liu Changhua Xu Xiaole Ding Guodong Wuhan Polytech Univ Sch Math & Comp Wuhan 430023 Peoples R China

ISBN: (纸本)9783038350019

With the development of computer and network technology, the pace of people's life is more and more fast. At the same time, the need in the entertainment is also growing. The game based on handheld is becoming more and more popular. It has been booming along with the development of its educational, fun, casual, easy to carry, easy to operate, highly interactive and many other features to meet the people's entertainment *** paper introduces the embedded systems based on general-purpose software development model and development process, including the design of hardware platform and software. The design of the hardware platform is the QuartusII10.1, the software platform is Nios II EDS 10.1 and the programming language is C and VHDL. Based on the SPOC Builder tool, we designed the reconfigurable IP cores of the VGA display, LTM touch screen. With Galaxian game as an example, we design a embedded game based on GUI. The results show that the game system is friendly human-computer interaction and quick response and action. This configurable IP core is highly flexibility, variability, plasticity and it can achieve more functional expansion and development in the same resource.

关键词： field-programmable gate array Galaxian game Configurable IP core System On a Programming Chip

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An Information-Theoretic Approach to Motor Action Decoding with a Reconfigurable Parallel Architecture

An Information-Theoretic Approach to Motor Action Decoding w...

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33rd Annual International Conference of the IEEE Engineering-in-Medicine-and-Biology-Society (EMBS)

作者： Craciun, Stefan Brockmeier, Austin J. George, Alan D. Lam, Herman Principe, Jose C. Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781424441228

Methods for decoding movements from neural spike counts using adaptive filters often rely on minimizing the mean-squared error. However, for non-Gaussian distribution of errors, this approach is not optimal for performance. Therefore, rather than using probabilistic modeling, we propose an alternate non-parametric approach. In order to extract more structure from the input signal (neuronal spike counts) we propose using minimum error entropy (MEE), an information-theoretic approach that minimizes the error entropy as part of an iterative cost function. However, the disadvantage of using MEE as the cost function for adaptive filters is the increase in computational complexity. In this paper we present a comparison between the decoding performance of the analytic Wiener filter and a linear filter trained with MEE, which is then mapped to a parallel architecture in reconfigurable hardware tailored to the computational needs of the MEE filter. We observe considerable speedup from the hardware design. The adaptation of filter weights for the multiple-input, multiple-output linear filters, necessary in motor decoding, is a highly parallelizable algorithm. It can be decomposed into many independent computational blocks with a parallel architecture readily mapped to a field-programmable gate array (FPGA) and scales to large numbers of neurons. By pipelining and parallelizing independent computations in the algorithm, the proposed parallel architecture has sublinear increases in execution time with respect to both window size and filter order.

关键词： Cost function Decoding Hardware Kernel MEE filter Neurons Parallel architectures Wiener filters adaptive filters adaptive filters alternate nonparametric approach analytic Wiener filter computational complexity field-programmable gate array hardware desig

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Local Spatio-Temporal Propagation Based Adaptive Model Generation and Update for High Frame Rate and Ultra-Low Delay Foreground Detection 26

Local Spatio-Temporal Propagation Based Adaptive Model Gener...

引用

IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Cai, Peikun Du, Songlin Ikenaga, Takeshi Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka Japan Southeast Univ Sch Automat Nanjing Peoples R China

ISBN: (纸本)9781728144030

High frame rate and ultra-low delay matching system plays an increasingly important role in human-machine interactive applications, which demands better experience and higher accuracy. Foreground detection is an indispensable preprocessing step to make the system suitable for complex scenes. Although many foreground detection algorithms have been proposed, few can achieve high speed in hardware due to their high complexity or high consumption. Based on the foreground detection algorithm ViBe, this paper proposes a local spatio-temporal propagation based adaptive model generation and update strategy for high frame rate and ultra-low delay foreground detection. Our algorithm predicts whether a region is a foreground by setting up detecting points, thereby adaptively adjusting the number of pixels that needs to be modeled. Secondly, the local linear illumination correlation is used to update models, which makes the algorithm more robust to illumination changes. The evaluation results show that the proposed algorithm successfully achieves real-time processing on the field-programmable gate array (FPGA) at a resolution of 640x480 pixels, with a delay of 0.908ms/frame.

关键词： foreground detection high frame rate ultra-low delay real-time processing field-programmable gate array

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Performance Study of Multi-tenant Cloud FPGAs

Performance Study of Multi-tenant Cloud FPGAs

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35th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Mbongue, Joel Mandebi Saha, Sujan Kumar Bobda, Christophe Univ Florida ECE Dept Gainesville FL 32611 USA

ISBN: (纸本)9781665435772

Cloud deployments now increasingly provision FPGA accelerators as part of virtual instances. While commercial clouds still essentially expose single-tenant FPGAs to the users, the growing demand for hardware acceleration raises the need for architectures supporting FPGA multi-tenancy. In this work, we explore the trade-off between hardware consolidation and performance. Experiments show that FPGA multi-tenancy increases hardware utilization and decreases IO performance in the order of microseconds compared to the single-tenant model. The experiments also demonstrate that implementing on-chip communication between the hardware workloads of a cloud user significantly reduces the overall communication overhead.

关键词： Cloud field-programmable gate array Multi-tenancy

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Improving Pathfinder Algorithm Perfomance for FPGA Routing

Improving Pathfinder Algorithm Perfomance for FPGA Routing

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Zapletina, Mariya A. Zheleznikov, Daniil A. Gavrilov, Sergey, V RAS Inst Design Problems Microelect Zelenograd Russia

ISBN: (纸本)9781665404761

The paper presents some algorithmic improvements to accelerate the routing stage for FPGA. One of the main advantages of FPGA is the high development speed;thereby the importance of efficient computer-aided design tools for modern FPGA is hard to overestimate. The placement and routing stages are crucial for the FPGA performance, and meanwhile they take up a significant part of the design time. The investigated base routing algorithm is the modified Pathfinder for the mixed routing resources graph. Pathfinder is a popular iterative negotiation-based router acting on the principle of eliminating nets congestions. Due to the proposed algorithmic improvements, such as ignoring the uncongested nets while ripup and rerouting stage, and some other, the summary routing time is reduced significantly. The observed average time decrease is from 1.3X to 2.6X depending on the FPGA architecture. The benchmarks ISCAS'85&89, LGSynth'89 and several real industrial circuits were used for testing.

关键词： field-programmable gate array congestion-aware routing routing acceleration Pathfinder modification shortest path search

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Continuous Live-Tracing as Debugging Approach on FPGAs

Continuous Live-Tracing as Debugging Approach on FPGAs

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Blochwitz, Christopher Klink, Raphael Joseph, Jan Moritz Pionteck, Thilo Univ Lubeck Inst Comp Engn D-23562 Lubeck Germany Otto Von Guericke Univ Inst Informat Technol & Commun D-39106 Magdeburg Germany

ISBN: (纸本)9781538637975

This work presents a new approach for monitoring and debugging RTL logic on FPGAs-Live-Tracing-Logic. The design combines the two most common approaches for debugging RTL logic, Scan-Chains and Trace-Buffers, while avoiding their disadvantage: First, slow and clock-controlled scans of the Scan-Chains, second, a limited time period for tracing of Trace-Buffers, respectively. The Live-Tracing-Logic connects trace-buffer modules serially, monitors signal events continuously, transmits the collected data to the host system via a high bandwidth PCIe interface, and converts the data into a VCD file. Furthermore, an automatic tool flow is introduced, which requires only two user interactions: First, using pragmas, second, starting a TCL script. The Live-Tracing-Logic is evaluated for different workloads and different tracing modes. The results show that the architecture has the capacity to continuously trace up to 3.10 GB/s of data and is only limited by the PCIe interface. Furthermore, the Live-Tracing-Logic is suitable for multi clock designs and utilizes up to 70% less resources in comparison to the Integrated Logic Analyzer of Xilinx.

关键词： Debugging Tracing Logic Analyzer Hardware field-programmable gate array

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A Convolutional Spiking Neural Network Accelerator with the Sparsity-aware Memory and Compressed Weights 35

A Convolutional Spiking Neural Network Accelerator with the ...

引用

35th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Liu, Hanqing Cui, Xiaole Zhang, Sunrui Yin, Mingqi Jiang, Yuanyuan Cui, Xiaoxin Peking Univ Shenzhen Grad Sch Shenzhen Peoples R China Peking Univ Beijing Peoples R China

ISBN: (纸本)9798350349641;9798350349634

The spiking neural network (SNN) has advantage in the edge AI applications for its spatiotemporal sparsity. The high energy efficiency is an important concern in the study of SNN accelerator designs. In this paper, a lightweight event-driven convolutional SNN accelerator that utilizes the sparsity of both the spike events and the network weights is proposed. In the event-driven mode, the proposed accelerator uses the compressed input spikes and a spike-oriented convolution data flow. An output spike compressor is also designed. To balance the computation performance and the memory space occupancy, a spike sparsity-aware memory scheme that automatically switches the spike format by a real-time monitoring strategy is designed. The compression memories and a buffer for network weights are designed to save the on-chip memory space. The accelerator prototype is verified on the Xilinx Virtex XCVU9P FPGA platform. It achieves an equivalent performance of 139.5GFLOPS on the N-MNIST dataset. Compared to the baseline using the same computational resources, the proposed accelerator can improve the inference performance, the inference energy efficiency and the memory space by 4.6, 3.6 and 1.6 times, respectively. The proposed accelerator has advantages in energy efficiency and hardware overhead compared to the previous works on the same hardware platform.

关键词： Neuralmorphic computing Spiking neural network accelerator Sparse spikes Sparse matrix compression field-programmable gate array

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HARDWARE IMPLEMENTATION OF THE DISCRETE FOURIER TRANSFORM WITH NON-POWER-OF-TWO PROBLEM SIZE

HARDWARE IMPLEMENTATION OF THE DISCRETE FOURIER TRANSFORM WI...

引用

2010 IEEE International Conference on Acoustics, Speech, and Signal Processing

作者： Milder, Peter A. Franchetti, Franz Hoe, James C. Pueschel, Markus Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

ISBN: (纸本)9781424442966

In this paper, we examine several algorithms suitable for the hardware implementation of the discrete Fourier transform (DFT) with non-power-of two problem size. We incorporate these algorithms into Spiral, a tool capable of automatically generating corresponding hardware implementations. We discuss how each algorithm can be used to generate different types of hardware structures, and we demonstrate that our tool is able to produce hardware implementations of non-power-of-two sized DFTs over a wide range of cost/performance tradeoff points.

关键词： Discrete Fourier transform high-level synthesis field-programmable gate array FPGA algorithms

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Convolution neural network development support system using approximation methods to evaluate inference accuracy and memory usage in an embedded system

Convolution neural network development support system using ...

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IEEE Conference on SmartWorld, Ubiquitous Intelligence and Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People and Smart City Innovation

作者： Matsumoto, Toki Nakamoto, Yukikazu Yamamoto, Ryota Honda, Shinya Wakabayashi, Kazutoshi Univ Hyogo Grad Sch Appl Informat Kobe Hyogo Japan Nagoya Univ Grad Sch Informat Nagoya Aichi Japan NEC Corp Ltd Kawasaki Kanagawa Japan

ISBN: (纸本)9781728140346

Convolution neural networks have become widely used in embedded systems such as automatic driving systems. In these cases, inference functions in convolution neural networks are implemented due to resource limitation in embedded systems. field-programmable gate array implementation is preferable because of low power consumption and real-time response time in embedded systems. Parameters in a convolution neural network are floating-point numbers, and enormous floating-point calculation is required. This is a challenge because the field-programmable gate array has a limited floating processing unit and in-memory processing. One way to solve the problem is to approximate an enormous number of parameters and to perform efficient computation. In the approximation, floating-point numbers of parameters are implemented using smaller-size integers or numbers having fewer bits. However, the inference accuracy decreases in the approximation, leading to a tradeoff situation. In addition, which layer should be approximated in order to be effective is not clear. In order to solve these problems, we developed an approximation support system. The developed system approximates the parameters and calculates the accuracy of the parameters and the required memory size. Furthermore, using this system, we carry out experiments to evaluate the effectiveness of several approximation methods for a large-scale network and dataset.

关键词： Convolution neural network field-programmable gate array embedded systems approximation

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High-Speed Frame Grabber for Track Monitoring Systems

High-Speed Frame Grabber for Track Monitoring Systems

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ASME/ASCE/IEEE Joint Rail Conference

作者： Liu, Yu-Wei Hsieh, Hsiang-Yu Chen, Nanming Natl Taiwan Univ Sci & Technol Dept Elect Engn Taipei Taiwan

ISBN: (纸本)9780791854594

In recent years, image recognition, along with improvements in image processing technology, has become a mainstream method of object inspection. The quality of images directly affects the image-recognition rate. Track monitoring systems play an important role in ensuring safety and preventing derailments of trains, on the basis of the prevailing track conditions. Therefore, the conditions of track systems are very important. In this research, a high-speed frame grabber system is designed. The triggering rate of its line scan camera can be adjusted to match the vehicle speed of the train, so that the pixels per inch of images captured by this camera are fixed. The hardware equipment of the designed system includes a line scan camera, an image acquisition card, artificial lightings, a contrast sensor, and a system on a programmable chip (SOPC) development board. An exposure time control system is designed on the basis of a field-programmable gate array (FPGA) core. The designed system can acquire clear high-speed images while the vehicle speed changes dramatically. The experimental results confirm the feasibility of using line scan cameras for railway vehicles.

关键词： line scan camera contrast sensor field-programmable gate array

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