检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

397 篇 期刊文献
160 篇 会议
11 篇 学位论文
2 篇 科技报告

馆藏范围

570 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

524 篇 工学
- 324 篇 电气工程
- 229 篇 计算机科学与技术...
- 70 篇 信息与通信工程
- 56 篇 仪器科学与技术
- 51 篇 电子科学与技术（可...
- 43 篇 软件工程
- 40 篇 控制科学与工程
- 21 篇 材料科学与工程（可...
- 18 篇 动力工程及工程热...
- 17 篇 机械工程
- 17 篇 石油与天然气工程
- 16 篇 核科学与技术
- 9 篇 生物医学工程（可授...
- 8 篇 交通运输工程
- 8 篇 环境科学与工程（可...
- 7 篇 测绘科学与技术
- 6 篇 光学工程
- 4 篇 力学（可授工学、理...
101 篇 理学
- 65 篇 物理学
- 21 篇 生物学
- 18 篇 化学
- 11 篇 数学
- 4 篇 地球物理学
- 2 篇 大气科学
32 篇 医学
- 20 篇 临床医学
- 9 篇 基础医学(可授医学...
- 4 篇 特种医学
17 篇 管理学
- 17 篇 管理科学与工程(可...
3 篇 教育学
- 2 篇 教育学
2 篇 法学
- 2 篇 法学
1 篇 艺术学

主题

570 篇 field-programmab...
78 篇 field programmab...
62 篇 fpga
25 篇 high-level synth...
16 篇 computer archite...
16 篇 digital signal p...
14 篇 hardware acceler...
13 篇 hardware
13 篇 convolutional ne...
12 篇 reconfigurable c...
11 篇 deep learning
11 篇 hardware impleme...
10 篇 embedded systems
9 篇 system-on-chip
8 篇 random access me...
8 篇 real-time system...
7 篇 internet of thin...
7 篇 graphics process...
7 篇 high-performance...
7 篇 time-to-digital ...

机构

5 篇 univ concepcion ...
4 篇 sejong univ dept...
4 篇 city univ hong k...
3 篇 birla inst techn...
3 篇 korea aerosp uni...
3 篇 univ florida dep...
3 篇 brno university ...
3 篇 korea aerosp uni...
3 篇 zhejiang univ co...
3 篇 imperial coll lo...
3 篇 univ so calif ct...
3 篇 natl cent univ d...
3 篇 univ alberta dep...
2 篇 sejong univ dept...
2 篇 karpagam coll en...
2 篇 fev europe gmbh ...
2 篇 kyushu inst tech...
2 篇 karabuk univ dep...
2 篇 natl taiwan univ...
2 篇 tokai univ toro ...

作者

8 篇 figueroa miguel
6 篇 suzuki daisuke
6 篇 hanyu takahiro
5 篇 gokdag mustafa
5 篇 torikai hiroyuki
5 篇 luk wayne
5 篇 gulbudak ozan
4 篇 andert jakob
4 篇 tamukoh hakaru
4 篇 cheung ray c. c.
4 篇 jung yunho
4 篇 lee seongjoo
4 篇 shimobaba tomoyo...
3 篇 song dong
3 篇 volkov m. v.
3 篇 singh vijay kuma...
3 篇 hung y. -c.
3 篇 ito tomoyoshi
3 篇 pinto armando n.
3 篇 amado sofia b.

语言

550 篇 英文
16 篇 其他
3 篇 中文
1 篇 俄文

检索条件"主题词=Field-programmable gate array"

共 570 条记录，以下是381-390 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks 16th

Improving Performance Estimation for FPGA-Based Accelerators...

引用

16th International Symposium on Applied Reconfigurable Computing

作者： Ferianc, Martin Fan, Hongxiang Chu, Ringo S. W. Stano, Jakub Luk, Wayne UCL Dept Elect & Elect Engn London England Imperial Coll London Dept Comp London England UCL Dept Comp Sci London England Swiss Fed Inst Technol Dept Informat Technol & Elect Engn Zurich Switzerland

ISBN: (纸本)9783030445331;9783030445348

field-programmable gate array (FPGA) based accelerators are being widely used for acceleration of convolutional neural networks (CNNs) due to their potential in improving the performance and reconfigurability for specific application instances. To determine the optimal configuration of an FPGA-based accelerator, it is necessary to explore the design space and an accurate performance prediction plays an important role during the exploration. This work introduces a novel method for fast and accurate estimation of latency based on a Gaussian process parametrised by an analytic approximation and coupled with runtime data. The experiments conducted on three different CNNs on an FPGA-based accelerator on Intel Arria 10 GX 1150 demonstrated a 30.7% improvement in accuracy with respect to the mean absolute error in comparison to a standard analytic method in leave-one-out cross-validation.

关键词： field-programmable gate array Deep learning Convolutional neural network Performance estimation Gaussian process

来源：评论

学校读者我要写书评

暂无评论

A Long-Range Hardware Bubble Corrector Technique for Short-Pulse-Width and Multiple-Registration Encoders 7

A Long-Range Hardware Bubble Corrector Technique for Short-P...

引用

7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Dept Elect & Elect Engn Bristol Avon England

ISBN: (纸本)9781665436977

Bubble detection and correction logic is vital in modern data capture devices to solve bubbles in the output thermometer codes due to non-linearities in the scale causing negative bin widths. Previous bubble correction techniques are either unsuitable for short pulse widths and multiple registration (ones-encoder) or have a very short range (all other methods). In this paper, we propose a hardware technique to detect and correct bubbles up to the length of the pulse width while preserving position information using a hybrid between the ones-encoder and a single stage of a modified insertion sort. This design was shown to meet timing on a Xilinx Artix-7 FPGA at 100 MHz or above using only 13% of the device, demonstrating hardware-viability. The design is also fully-pipelined to demonstrate high bandwidths. The limitations of the algorithm are stated and some possible improvements are suggested.

关键词： Hardware field-programmable gate array Bubble Correction Converters Encoders Thermometer Code Population Counter

来源：评论

学校读者我要写书评

暂无评论

Hardware-Accelerated Index Construction for Semantic Web 17

Hardware-Accelerated Index Construction for Semantic Web

引用

17th International Conference on field-programmable Technology (FPT)

作者： Blochwitz, Christopher Wolff, Julian Berekovic, Mladen Heinrich, Dennis Groppe, Sven Joseph, Jan Moritz Pionteck, Thilo Univ Lubeck Inst Comp Engn D-23562 Lubeck Germany Univ Lubeck Inst Informat Syst D-23562 Lubeck Germany Otto von Guericke Univ Inst Informat Technol & Commun D-39106 Magdeburg Germany

ISBN: (纸本)9781728102139

In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardware engine for index construction are presented. We propose an FPGA-centric design, which we call Hardware-Triplestore. As part of the design, a scalable and parallel architecture for Triplestore construction is introduced. We propose a hybrid data structure consisting of three layers, one for every element of the semantic triple. The data structure is optimized for our hardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately from the rest of the database system and achieves an insertion rate of 1.24 million triples per second, which is 17 times faster than one of the fastest software Triplestore-RDF-3X-.

关键词： Triplestore RDF-3X Semantic Web Database Hardware field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

FPGA implementation of real-time fluorescence endoscopy imaging algorithms

FPGA implementation of real-time fluorescence endoscopy imag...

引用

International Conference on Biomedical and Pharmaceutical Engineering

作者： Sing, Cheong Lee Soon, Seah Hock Feng, Lin Kenneth, Yu Chin-Wen Kemao, Qian Chee, Soo Khee Thong, Patricia Olivo, Malini Nanyang Technol Univ Bioinformat Res Ctr Singapore Singapore Nanyang Technol Univ Sch Comp Engn Singapore Singapore Nanyang Technol Univ Sch Biol Sci Singapore Singapore Nanyang Technol Univ Div Med Sci Singapore Singapore

ISBN: (纸本)9789810579432

Fluorescence endoscopy is a novel imaging technique that offers a non-invasive means to diagnose and stage cancers without the need to conduct biopsies of suspected lesions. Work carried out by our research group showed that fluorescence diagnosis can be further enhanced by incorporating a ratio diagnostic algorithm in the system. Currently images captured using these imaging techniques have to be processed and analyzed off-line, adding a delay to the diagnosis process. We aim to develop a real-time image processing and analysis system to be used with fluorescence endoscopy for early diagnosis and staging of oral and bladder cancers. Fast capturing of suspicious features implied by the fluorescence images provides a means for efficient communication, and an optimized and focused in vivo imaging process. The ultimate aim is to provide an accurate, sensitive and non-invasive real-time cancer diagnosis and staging system that can be used in an outpatient clinical setting. In this paper, we describe the framework of such an imaging system, as well as the initial algorithm development and implementation with the field-programmable gate arrays.

关键词： field-programmable gate array fluorescence endoscopy real-time image processing medical imaging

来源：评论

学校读者我要写书评

暂无评论

Challenges Designing for FPGAs Using High-Level Synthesis

Challenges Designing for FPGAs Using High-Level Synthesis

引用

IEEE High Performance Extreme Computing Virtual Conference (HPEC)

作者： Faber, Clayton J. Harris, Steven D. Xiao, Zhili Chamberlain, Roger D. Cabrera, Anthony M. Washington Univ St Louis McKelvey Sch Engn St Louis MO USA Oak Ridge Natl Lab Architectures & Performance Grp Oak Ridge TN USA

ISBN: (数字)9781665497862

ISBN: (纸本)9781665497862

High-Level Synthesis (HLS) tools are aimed at enabling performant FPGA designs that are authored in a high-level language. While commercial HLS tools are available today, there is still a substantial performance gap between most designs developed via HLS relative to traditional, labor intensive approaches. We report on several cases where an anticipated performance improvement was either not realized or resulted in decreased performance. These include: programming paradigm choices between data parallel vs. pipelined designs;dataflow implementations;configuration parameter choices;and handling odd data set sizes. The results point to a number of improvements that are needed for HLS tool flows, including a strong need for performance modeling that can reliably guide the compilation optimization process.

关键词： HLS FPGA High-Level Synthesis field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Transparent Broadband VPN gateway: Achieving 0.39 Tbps per Tunnel with Bump-in-the-Wire

Transparent Broadband VPN Gateway: Achieving 0.39 Tbps per T...

引用

IEEE Conference on Computer Communications (IEEE INFOCOM)

作者： Tanaka, Kenji Uchida, Takashi Matsuda, Yuki Arikawa, Yuki Kaji, Shinya Sakamoto, Takeshi NTT Corp Tokyo Japan Fixstars Tokyo Japan

ISBN: (纸本)9798350383515;9798350383508

The demand for virtual private networks (VPNs) that provide confidentiality, integrity, and authenticity of communications is growing every year. IPsec is one of the oldest and most widely used VPN protocols, implemented between the internet protocol (IP) layer and the data link layer of the Linux kernel. This implementation method, known as bump-in-the-stack, has the advantage of being able to transparently apply IPsec to traffic without changing the application. However, its throughput efficiency (Gbps/core) is worse than regular Linux communication. Therefore, we chose the bump-in-the-wire (BITW) architecture, which handles IPsec in hardware separate from the host. Our proposed BITW architecture consists of inline cryptographic accelerators implemented in field-programmable gate arrays and a programmable switch that connects multiple such accelerators. A VPN gateway implemented with our architecture is transparent and improves the throughput efficiency by 3.51 times and power efficiency by 3.40 times over a VPN gateway implemented in the Linux kernel. It also demonstrates excellent scalability, and has been confirmed to scale to a maximum of 386.24 Gbps per tunnel, exceeding state-of-the-art technology in maximum throughput and efficiency per tunnel. In multiple-tunnels use cases, the proposed architecture improves the energy efficiency by 2.49 times.

关键词： VPN IPsec programmable Switches field-programmable gate array Bump-in-the-wire

来源：评论

学校读者我要写书评

暂无评论

Dynamic correction of the laser beam distortion by 2000 Hz FPGA-based adaptive optical system 9

Dynamic correction of the laser beam distortion by 2000 Hz F...

引用

Conference on Laser Communication and Propagation through the Atmosphere and Oceans IX held at SPIE Optical Engineering + Applications Conference

作者： Nikitin, A. N. Starikov, F. A. Volkov, M. V. Bogachev, V. A. Khlebnikov, A. A. Rukosuev, A. L. Inst Geosphere Dynam IDG RAS Them Academician MA Moscow Russia Inst Laser Phys ILFI RFNC VNIIEF Sarov Russia

ISBN: (数字)9781510638198

ISBN: (纸本)9781510638198;9781510638181

The results of numerical simulations and experiments on the correction of turbulent distortions of a laser beam are presented. The experiments were carried out using an adaptive optical system with a bandwidth of 2000 Hz. It was shown that for effective correction the bandwidth of the adaptive optical system should be an order of magnitude larger than the bandwidth of turbulent distortions.

关键词： high-speed adaptive optical system laser wavefront deformable mirror turbulence field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Hardware Architectures for Computing 8-Point Cosine Number Transform

Hardware Architectures for Computing 8-Point Cosine Number T...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： de Oliveira Neto, Jose R. Lima, Juliano B. Univ Fed Pernambuco Dept Elect & Syst Recife PE Brazil

ISBN: (纸本)9781538648810

The cosine number transform (CNT) is a cosine-like number-theoretic transform, which has been employed as the basis for multimedia security schemes. In this paper, we propose hardware architectures for computing an 8-point CNT. The architectures include a pipelined approach and are based on a recently introduced fast algorithm, which has been demonstrated to be more efficient than the direct computation of the CNT. We quantify such an efficiency by considering several aspects inherent to modular arithmetic and comparing metrics obtained from field-programmable gate array (FPGA) implementations of the proposed architectures.

关键词： Number-theoretic transforms cosine number transform hardware architectures pipeline field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Synthesizing Efficient Hardware from High-Level Functional Hardware Description Languages 26

Synthesizing Efficient Hardware from High-Level Functional H...

引用

26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Shahmohammadian, Mahshid Mainland, Geoffrey Drexel Univ Dept Comp Sci Philadelphia PA 19104 USA

ISBN: (纸本)9781728109961

Functional hardware description languages (FHDL) provide powerful tools for building new abstractions that enable sophisticated hardware system to be constructed by composing small reusable parts. Raising the level of abstractions in hardware designs means the programmer can focus on high-level circuit structure rather than mundane low-level details. The language features that facilitate this include high-order functions, rich static type system with type inference, and parametric polymorphism. We use hand-written structural and behavioral VHDL, Simulink, and the Kansas Lava FHDL to re-implement several components taken from a Simulink model of an orthogonal frequency-division multiplexing (OFDM) physical layer (PHY). Our development demonstrates that an FHDL can require fewer lines of code than traditional design languages without sacrificing performance.

关键词： circuit generation functional hardware description languages high-level hardware design field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

An Efficient Algorithm Strategy for Synchronous Rectification used in LLC Resonant Converters 42

An Efficient Algorithm Strategy for Synchronous Rectificatio...

引用

42nd Annual Conference of the IEEE-Industrial-Electronics-Society (IECON)

作者： Hong, Liang Ma, Hao Wang, Jun Du, Jianhua Wang, Binlei Zhejiang Univ Coll Elect Engn Hangzhou 310027 Peoples R China Beijing Inst Control Engn Beijing 100190 Peoples R China

ISBN: (纸本)9781509034741

In this paper, an efficient algorithm strategy for synchronous rectification (SR) used in LLC resonant converters is proposed. The output voltage and the primary resonant inductor current of LLC converter are combined together to produce suitable drive signals for SR in the below resonance mode. In the other resonance modes, the drive signals for SR are synchronous with the drive signals of corresponding primary switches. In order to validate the feasibility of the proposed algorithm strategy, a 300W prototype with 100V input voltage, 25V output voltage is implemented using field-programmable gate array (FPGA). The measured maximum efficiency is 92.1% and the overall efficiency is higher than the one with conventional drive method for SR.

关键词： algorithm strategy LLC resonant converters field-programmable gate array synchronous rectification

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共57页 << < 35 36 37 38 39 40 41 42 43 44 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：