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5th International Conference on Computer and Technology Applications (ICCTA)

作者： Wang, Meile Zhang, Zhizhong Wang, Guangya Chongqing Univ Posts & Telecommun 2 Chongwen Rd Chongqing Peoples R China

ISBN: (纸本)9781450371810

The design of the baseband board for many types of instrumentation developed is limited to verify its feasibility by implementation. On this basis we propose a detailed feasibility analysis method before the design of the baseband board to prevent the waste of the manpower and time resources because of the shortage of chip resources, which provided a reference for the design of the baseband board. Firstly we determine the model of core processor based on LTE-A characteristics and baseband board requirements;then we focus on the storage capacity and bus capacity of the baseband board to ensure that the selected components have sufficient capacity and margin;fmally we prove the correctness of the feasibility analysis through the test on the baseband board, and it also provides the reference for other hardware chip selection.

关键词： field-programmable gate array feasibility LTE-A baseband board

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field-programmable gate array Implementation of a Single Photon-Counting Receive Modem

Field-Programmable Gate Array Implementation of a Single Pho...

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作者： Brian E Vyhnalek Jennifer N Downey Daniel J Zeleznikar Nicholas C Lantz Michael A Marsden William P Simon Thomas P Bizon

modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver

关键词： field-programmable gate array Pulse Position Modulation Decoding Concatenated Codes Timing Recovery Optical Receiver Iterative decoder

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Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

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JOURNAL OF ELECTRONIC IMAGING 2017年第1期26卷 013005-013005页

作者： Mostafa, Sheikh Shanawaz Natercia Sousa, L. Ferreira, Nuno Fabio Sousa, Ricardo M. Santos, Joao Wany, Martin Morgado-Dias, F. Univ Lisbon Inst Super Tecn Ave Rovisco Pais 1 P-1049001 Lisbon Portugal Madeira Interact Technol Inst Polo Cient & Tecnol Madeira Floor 2 P-9020105 Funchal Portugal Univ Madeira Colegio Jesuitas Praca MunicipioRua Ferreiros P-9000082 Funchal Portugal AWAIBA CMOSIS PORTUGAL Madeira Tecnopolo P-9020105 Funchal Portugal

Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm x 1 mm x 1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA. (C) 2017 SPIE and IS&T

关键词： endoscopic camera image processing field-programmable gate array high frame rate

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Time-of-flight ranging method by measuring pulse laser phase based on field-programmable gate array digital mixing

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MEASUREMENT SCIENCE AND TECHNOLOGY 2021年第2期32卷

作者： Tao, Min Gong, Xiaobin Hou, Yu Li, Baohua Song, Junfeng Chen, Jian Gao, Fengli Jilin Univ Coll Elect Sci & Engn State Key Lab Integrated Optoelect Changchun 130012 Peoples R China ShanheGensheng Technol Co Ltd Jilin Prov Jilin 132011 Jilin Peoples R China

We propose a time-of-flight ranging method by measuring the pulse laser phase based on field-programmable gate array (FPGA) digital mixing, in which accurate laser ranging with a total digital system is realized by combining one FPGA chip with a simple laser transmitting and receiving circuit. The system has the advantage of simple structure, reliable operation, low manufacturing cost and easy integration. Experimental results show that compared with the pulse laser ranging method using commercial time-to-digital converter chips, it can realize precise measurement of distance, and the measurement error can be significantly reduced. In addition, this method has better performance of ranging accuracy.

关键词： time-of-flight laser ranging field-programmable gate array digital mixing

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A fine-grained programmable logic module with small amount of configuration data for dynamically reconfigurable field-programmable gate array

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JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 2003年第4B期42卷 2167-2170页

作者： Miyamoto, N Karnan, L Kotani, K Ohmi, T Tohoku Univ Grad Sch Engn Dept Elect Engn Aoba Ku Sendai Miyagi 9808579 Japan Tohoku Univ New Ind Creat Hatchery Ctr Aoba Ku Sendai Miyagi 9808579 Japan

Dynamically customizable and reconfigurable hardware architecture for a specific task on demand is one of the most important issues to-bring out a novel-computing paradigm in the era of system LSIs. Our target is, to realize a flexible processor. which is a kind of dynamically reconfigurable field-programmable gate array (FPGA) and is able to execute signal processing While reading the next configuration data (CD) simultaneously. In order to realize the flexible processor, since the amount of CD is enormous in conventional FPGAs, it is necessary to reduce the amount of CD as much as possible. In this paper, we propose a newly developed programmable logic module that can reduce the amount of CD to no less than 86% of that for the conventional Look Up Table (LUT)-based programmable logic module.

关键词： dynamically reconfigurable processor field-programmable gate array small configuration data amount fine grain programmable logic module

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NIWAS: A non-interactive watermark authentication scheme for industrial field-programmable gate array designs

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ADVANCES IN MECHANICAL ENGINEERING 2018年第6期10卷

作者： Long, Jing Zhang, Dafang Liang, Wei Ning, Zuoting Zhang, Qingyong Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Hunan Peoples R China Xiamen Univ Technol Sch Optoelect & Commun Engn Xiamen Peoples R China Hunan Police Acad Hunan Prov Key Lab Network Invest Technol Changsha Hunan Peoples R China Fujian Univ Technol Sch Mech & Automot Engn Fuzhou Fujian Peoples R China

Except the network attacks, the industrial networked devices in Internet of things are also threatened by intellectual property infringement. Watermarking technique is a prevalent way to avoid this threat. Previous work on authenticating a watermark in industrial intellectual properties easily discloses sensitive information of real embedded watermarks. In this case, the evidence of identifying the ownership of industrial intellectual property may be attacked by the illegal verifiers. Although several watermark detection techniques can address the disclosure of sensitive information in detection procedure, the efficiency of detection is relatively low. Besides, it may yield large communication overhead of multiple authentication rounds. Motivated by the needs of robustness and efficiency, this work proposed a zero-knowledge approach to authenticate ownership of field-programmable gate array intellectual property design in industrial environment, named NIWAS. The prover can convince the verifier that he knows a secret in the suspected intellectual property design via only one interaction. Real locations of watermarks are concealed through location obfuscation. With the received authentication package from the prover, the verifier cannot obtain other useful information about the watermarks. The experiments show that NIWAS achieves high efficiency and robustness of watermark detection.

关键词： Intellectual property Internet of things field-programmable gate array zero-knowledge robustness

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Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications

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IEICE ELECTRONICS EXPRESS 2013年第23期10卷 20130772-20130772页

作者： Suzuki, Daisuke Natsui, Masanori Mochizuki, Akira Miura, Sadahiko Honjo, Hiroaki Kinoshita, Keizo Sato, Hideo Ikeda, Shoji Endoh, Tetsuo Ohno, Hideo Hanyu, Takahiro Tohoku Univ Ctr Spintron Integrated Syst Aoba Ku Sendai Miyagi 9808577 Japan Tohoku Univ Elect Commun Res Inst Aoba Ku Sendai Miyagi 9808577 Japan NEC Corp Ltd Green Platform Res Labs Tsukuba Ibaraki 3058501 Japan Tohoku Univ Grad Sch Engn Aoba Ku Sendai Miyagi 9808579 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Aoba Ku Sendai Miyagi 9800845 Japan Tohoku Univ WPI Adv Inst Mat Res Aoba Ku Sendai Miyagi 9808577 Japan

A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 x 20 2D-array is fabricated by 90 nm CMOS and 70 nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal data are still remained in the MTJ devices even when the power supply is cut off, standby power dissipation is completely eliminated by utilizing tile-level power gating. Power reduction is further accelerated by skipping wasted write operations of nonvolatile flip-flops (NVFFs) for storing temporal data when the temporal data and the stored one are the same. As a typical application, a motion-vector prediction function is implemented on the proposed NVFPGA, which results in a write power reduction of 77% compared to that of a conventional MTJ-based NVFPGA and a total power reduction of 70% compared to that of an SRAM-based FPGA.

关键词： field-programmable gate array magnetic tunnel junction device nonvolatile logic-in-memory architecture power-gating

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The concept of multicore computing and processing in a field-programmable gate array chip

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Procedia Computer Science 2024年 246卷 2400-2409页

作者： Paweł Poczekajło Łukasz Gołka Robert Suszyński Patryk Widuliński Koszalin University of Technology. ul Śniadeckich 2 75-453 Koszalin Poland

The article concerns the issue of multicore processing and implementation. The topic is introduced considering the functional division of various architectures. Examples of large-scale multicore architectures (with 144 and 1024 computational cores) are also presented. The main goal of the authors is to present the concept of implementing a multicore architecture in a field-programmable gate array (FPGA). An available solution of the Nios II processor from the Intel library in the Quartus environment is presented. Additionally, the authors discuss their own concept of a computational core, outlining key assumptions, advantages and disadvantages, as well as potential issues.

关键词： multicore multicore processing multi-ALU hardware implementation computational core implementation field-programmable gate array FPGA concept

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Exploration of preprocessing architectures for field-programmable gate array-based thermal-visual smart camera

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JOURNAL OF ELECTRONIC IMAGING 2016年第4期25卷 041006-041006页

作者： Imran, Muhammad Rinner, Bernhard Zand, Sajjad Zandi O'Nils, Mattias Mid Sweden Univ Dept Elect Design Holmgatan 10 S-85170 Sundsvall Sweden Alpen Adria Univ Inst Networked & Embedded Syst Lakeside Pk B02b A-9020 Klagenfurt Austria

Embedded smart cameras are gaining in popularity for a number of real-time outdoor surveillance applications. However, there are still challenges, i.e., computational latency, variation in illumination, and occlusion. To solve these challenges, multimodal systems, integrating multiple imagers can be utilized. However, trade-off is more stringent requirements on processing and communication for embedded platforms. To meet these challenges, we investigated two low-complexity and high-performance preprocessing architectures for a multiple imagers' node on a field-programmable gate array (FPGA). In the proposed architectures, majority of the tasks are performed on the thermal images because of the lower spatial resolution. Analysis with different sets of images show that the system with proposed architectures offers better detection performance and can reduce output data from 1.7 to 99 times as compared with full-size images. The proposed architectures can achieve a frame rate of 53 fps, logics utilization from 2.1% to 4.1%, memory consumption 987 to 148 KB and power consumption in the range of 141 to 163 mW on Artix-7 FPGA. This concludes that the proposed architectures offer reduced design complexity and lower processing and communication requirements while retaining the configurability of the system. (C) 2016 SPIE and IS&T.

关键词： smart camera preprocessing architecture thermal field-programmable gate array

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Real-time field-programmable gate array-based closed-loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia

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CNS NEUROSCIENCE & THERAPEUTICS 2024年第3期30卷 e14638-e14638页

作者： Kumar, Gajendra Zhou, Zhanhong Wang, Zhihua Kwan, Kin Ming Tin, Chung Ma, Chi Him Eddie City Univ Hong Kong Dept Neurosci Hong Kong Peoples R China City Univ Hong Kong Dept Biomed Engn Hong Kong Peoples R China Chinese Univ Hong Kong Ctr Cell & Dev Biol Sch Life Sci Hong Kong Peoples R China Chinese Univ Hong Kong State Key Lab Agrobiotechnol Hong Kong Peoples R China City Univ Hong Kong Dept Neurosci Tat Chee Ave Hong Kong Peoples R China

Aims: The open-loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real-time field-programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC-specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits. Methods: We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open-loop DCN-DBS or closed-loop DCN-DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real-time computation, was used for closed-loop DCN-DBS system. Results: Closed-loop DCN-DBS was triggered only when symptomatic muscle EMG was detected in a real-time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed-loop DCN-DBS was more effective than an open-loop paradigm as it reduced the frequency of DBS. Conclusion: Our real-time FPGA-based DCN-DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders.

关键词： cerebellar ataxia cerebellum deep brain stimulation electroencephalography electromyography field-programmable gate array

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