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检索条件"主题词=Field-programmable gate array"

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Optimizing CNN-Based Hyperspectral Image Classification on FPGAs 15th

Optimizing CNN-Based Hyperspectral Image Classification on F...

引用

15th International Symposium on Applied Reconfigurable Computing

作者： Liu, Shuanglong Chu, Ringo S. W. Wang, Xiwei Luk, Wayne Imperial Coll London Dept Comp London England UCL Dept Comp Sci London England China Acad Space Technol Beijing Peoples R China

ISBN: (纸本)9783030172268;9783030172275

Hyperspectral image (HSI) classification has been widely adopted in remote sensing imagery analysis applications which require high classification accuracy and real-time processing speed. Convolutional neural networks (CNNs)-based methods have been proven to achieve state-of-the-art accuracy in classifying HSIs. However, CNN models are often too computationally intensive to achieve real-time response due to the high dimensional nature of HSI, compared to traditional methods such as Support Vector Machines (SVMs). Besides, previous CNN models used in HSI are not specially designed for efficient implementation on embedded devices such as FPGAs. This paper proposes a novel CNN-based algorithm for HSI classification which takes into account hardware efficiency and thus is more hardware friendly compared to prior CNN models. An optimized and customized architecture which maps the proposed algorithm on FPGA is then proposed to support real-time on-board classification with low power consumption. Implementation results show that our proposed accelerator on a Xilinx Zynq 706 FPGA board achieves more than 70x faster than an Intel 8-core Xeon CPU and 3x faster than an NVIDIA GeForce 1080 GPU. Compared to previous SVM-based FPGA accelerators, we achieve comparable processing speed but provide a much higher classification accuracy.

关键词： Hyperspectral image classification Deep learning Convolution neural network field-programmable gate array

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Real-Time EEG Acquisition System for FPGA-based BCI 37

Real-Time EEG Acquisition System for FPGA-based BCI

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37th Conference on Design of Circuits and Integrated Circuits (DCIS)

作者： Eneriz, Daniel Medrano, Nicolas Calvo, Belen Caren Hernandez-Ruiz, Ana Antolin, Diego Univ Zaragoza Aragon Inst Engn Res I3A Grp Elect Design Zaragoza Spain Univ Zaragoza La Almunia Politech Sch Dept Elect Grp Elect Design La Almunia De Dona Godin Spain

ISBN: (数字)9781665459501

ISBN: (纸本)9781665459501

Multichannel electroencephalograph (EEG) signals data acquisition is non-invasive and easy to implement, thus being the preferred brain-related information carriers for Brain Computer Interfaces (BCIs). Since BCIs must be capable of processing information in real-time, their implementation in edge devices is currently being boosted, particularly on fieldprogrammable gate arrays (FPGA). In this work, a real-time EEG acquisition system based on the XADC of the Xilinx Zynq FPGA is presented, meeting the requirements of a well-known BCI processing algorithm, the EEGNet. Performed tests show minimal error in the acquisition, whose effects in the EEGNet accuracy are negligible.

关键词： Electroencephalograph Brain-Computer Interfaces field-programmable gate array Real-Time Acquisition

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Architecture Support for FPGA Multi-tenancy in the Cloud 31

Architecture Support for FPGA Multi-tenancy in the Cloud

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31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Mbongue, Joel Mandebi Shuping, Alex Bhowmik, Pankaj Bobda, Christophe Univ Florida ECE Dept Gainesville FL 32611 USA

ISBN: (纸本)9781728171470

Cloud deployments now increasingly provision FPGA accelerators as part of virtual instances. While FPGAs are still essentially single-tenant, the growing demand for hardware acceleration will inevitably lead to the need for methods and architectures supporting FPGA multi-tenancy. In this paper, we propose an architecture supporting space-sharing of FPGA devices among multiple tenants in the cloud. The proposed architecture implements a network-on-chip (NoC) designed for fast data movement and low hardware footprint. Prototyping the proposed architecture on a Xilinx Virtex Ultrascale+ demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization (we achieved 6x higher FPGA utilization with our case study), which is one of the major goals of virtualization. Overall, our NoC interconnect achieved about 2x higher maximum frequency than the state-of-the-art and a bandwidth of 25.6 Gbps.

关键词： Cloud field-programmable gate array Network-on-chip Multi-tenancy Elasticity

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Low Cost Resilient Regular Expression Matching on FPGAs 29

Low Cost Resilient Regular Expression Matching on FPGAs

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29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

作者： Leipnitz, Marcos T. de Souza, Eduardo Nunes Nazar, Gabriel L. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781509036233

The Network Function Virtualization (NFV) paradigm promises to make networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, field-programmable gate arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for FPGAs, soft errors on the configuration memory are a significant dependability threat. Therefore, in this work we evaluate the effects of configuration faults on the functionality of FPGA-based regular expression matching engines and propose fault tolerance mechanisms to improve its resilience against such faults.

关键词： Network Function Virtualization field-programmable gate array Regular Expression Matching Fault Tolerance

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Application-specific processor architecture: Then and now

Application-specific processor architecture: Then and now

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17th IEEE International Conference on Application-Specific Systems, Architectures and Processors

作者： Cappello, Peter Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasingly similar to those of systolic arrays. We then describe some economic and technological forces that are changing the landscape of architectural research. At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability. We describe a 2D architectural taxonomy, identifying what, we believe, to be a "sweet spot" for architectural research.

关键词： application-specific processor computer architecture field-programmable gate array FPGA general-purpose processor processor array systolic array taxonomy

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Dual-loop Control Scheme with Optimized Type-III Controller based on Genetic Algorithm for 6-phase Interleaved Converter in Electric Vehicle Drivetrains 22

Dual-loop Control Scheme with Optimized Type-III Controller ...

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22nd European Conference on Power Electronics and Applications (EPE ECCE Europe)

作者： Tran, Dai-Duong Chakraborty, Sajib Geury, Thomas Van Mierlo, Joeri El Baghdadi, Mohamed Hegazy, Omar Vrije Univ Brussel Pleinlaan 2 B-1050 Brussels Belgium Flanders Make B-3001 Heverlee Belgium

ISBN: (纸本)9789075815368

This paper presents an optimization procedure using a genetic algorithm (GA) for the dual-loop control scheme based on type-III controllers in a 6-phase interleaved converter. Four different objective functions (i.e. integration of squared and absolute errors and their time-weighted variants) are selected as the fitness functions of the GA. Based on the optimization procedure, step and dynamic responses of current and voltage controllers are investigated for those objective functions in terms of overshoot and settling time. In this study, another approach called classical 'k-factor' is utilized as a benchmark for the proposed type-III controller. Furthermore, two experimental tests are performed on a 60kW SiC-based prototype to verify the controller performances. The obtained results have demonstrated that the optimized controller design exhibits better dynamic response compared to the conventional counterpart.

关键词： Non-isolated interleaved DC/DC converter Optimization algorithm Small-signal average model Genetic algorithm field-programmable gate array

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A High Resolution FPGA-based Merged Delay Line TDC with Nonlinearity Calibration

A High Resolution FPGA-based Merged Delay Line TDC with Nonl...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Chen, Yuan-Ho Chung Yuan Christian Univ Dept Informat & Comp Engn Chungli Taiwan

ISBN: (纸本)9781467357623;9781467357609

This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 5 0 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) can be reduced 1 6 : 6 % and 5 : 4 % as compared with traditional one, respectively. Furthermore, 2 9 ps root-mean-square (RMS) is measured for the proposed MDL-TDC inputting a constant delay source. Therefore, the proposed MDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.

关键词： Time-to-digital converter field-programmable gate array Differential non-linearity Merged delay line

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Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA 29

Hybrid Dot-Product Calculation for Convolutional Neural Netw...

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29th International Conference on field-programmable Logic and Applications (FPL)

作者： Vestias, Mario Duarte, Rui Policarpo de Sousa, Jose T. Neto, Horacio Inst Politecn Lisboa INESC ID ISEL Lisbon Portugal Univ Lisbon INESC ID Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9781728148847

Convolutional Neural Networks (CNN) are quite useful in edge devices for security, surveillance, and many others. Running CNNs in embedded devices is a design challenge since these models require high computing power and large memory storage. Data quantization is an optimization technique applied to CNN to reduce the computing and memory requirements. The method reduces the number of bits used to represent weights and activations, which consequently reduces the size of operands and of the memory. The method is more effective if hybrid quantization is considered in which data in different layers may have different bit widths. This article proposes a new hardware module to calculate dot-products of CNNs with hybrid quantization. The module improves the implementation of CNNs in low density FPGAs, where the same module runs dot-products of different layers with different data quantizations. We show implementation results in ZYNQ7020 and compare with state-of-the-art works. Improvements in area and performance are achieved with the new proposed module.

关键词： Deep learning Convolutional Neural Network Embedded computing Hybrid quantization field-programmable gate array

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Building Your Own Trusted Execution Environments Using FPGA 19

Building Your Own Trusted Execution Environments Using FPGA

引用

19th ACM Asia Conference on Computer and Communications Security (ACM AsiaCCS)

作者： Armanuzzaman, Md Sadeghi, Ahmad-Reza Zhao, Ziming Univ Buffalo CactiLab Buffalo NY 14260 USA Tech Univ Darmstadt Darmstadt Germany

ISBN: (纸本)9798400704826

Despite of their benefits, existing Trusted Execution Environments (TEE) or enclaves have been criticized for lack of transparency, vulnerabilities, and various restrictions. A significant limitation is that they only provide a static and fixed hardware Trusted Computing Base (TCB) that cannot be customized for different applications. The design violates the principle of least privilege by including unnecessary peripherals in the hardware TCB and buggy peripheral drivers in the software TCB. Additionally, Existing TEEs time-share a processor core with the Rich Execution Environment (REE), making execution less efficient and vulnerable to cache side-channel attacks. Although many previous projects have focused on addressing software issues in TEEs on SGX, TrustZone, or RISC-V, some TEE issues are inherent in the hardware system's design, making them impossible to resolve with software alone. In this paper, we present BYOTee (Build Your Own Trusted Execution Environments), which is an easy-to-use hardware and software co-design infrastructure for building enclaves using field programmable gate arrays (FPGA). BYOTee creates enclaves with customized hardware TCBs and establishes a dynamic root of trust that allows untampered execution of Security-Sensitive Applications (SSA) from preexisting software on the hardcore system. Additionally, BYOTee provides mechanisms to attest the integrity of enclaves' hardware and software stacks. We implement a BYOTee system for the Xilinx System-on-Chip (SoC) FPGA. The evaluations on the low-end Zynq-7000 system for four SSAs and 12 benchmark applications demonstrate the usage, security, effectiveness, and performance of the BYOTee framework.

关键词： Trusted execution environment field-programmable gate array

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A Cost-Effective Baugh-Wooley Approximate Multiplier for FPGA-based Machine Learning Computing 6

A Cost-Effective Baugh-Wooley Approximate Multiplier for FPG...

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6th International Conference on AI Circuits and Systems (AICAS)

作者： Vakili, Shervin Inst Natl Rech Sci Energie Mat Telecommun Res Ctr Montreal PQ Canada

ISBN: (纸本)9798350383638;9798350383645

Deep learning hardware accelerators commonly incorporate a substantial quantity of multiplier units. Yet, the considerable complexity of multiplier circuits renders them a bottleneck, contributing to increased costs and latency. Approximate computing proves to be an effective strategy for mitigating the overhead associated with multipliers. This paper introduces an original approximation technique for signed multiplication on FPGAs. The approach involves a novel segmentation method applied to the Baugh-Wooley multiplication algorithm. Each segment is optimally accommodated within look-up table resources of modern AMD-Xilinx FPGA families. The paper details the design of an INT8 multiplier using the proposed approach, presenting implementation results and accuracy assessments for the inference of benchmark deep learning models. The implementation results reveal significant savings of 53.6% in LUT utilization compared to the standard INT8 Xilinx multiplier. Accuracy measurements conducted on four popular deep learning benchmarks show an average accuracy degradation of 4.8% in post-training deployment and 0.7% after retraining. The source code for this work is available on GitHub(1).

关键词： approximate multiplier field-programmable gate array machine learning computing

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