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检索条件"主题词=Field-programmable gate array"

共 571 条记录，以下是401-410 订阅

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A Cost-Effective Baugh-Wooley Approximate Multiplier for FPGA-based Machine Learning Computing 6

A Cost-Effective Baugh-Wooley Approximate Multiplier for FPG...

引用

6th International Conference on AI Circuits and Systems (AICAS)

作者： Vakili, Shervin Inst Natl Rech Sci Energie Mat Telecommun Res Ctr Montreal PQ Canada

ISBN: (纸本)9798350383638;9798350383645

Deep learning hardware accelerators commonly incorporate a substantial quantity of multiplier units. Yet, the considerable complexity of multiplier circuits renders them a bottleneck, contributing to increased costs and latency. Approximate computing proves to be an effective strategy for mitigating the overhead associated with multipliers. This paper introduces an original approximation technique for signed multiplication on FPGAs. The approach involves a novel segmentation method applied to the Baugh-Wooley multiplication algorithm. Each segment is optimally accommodated within look-up table resources of modern AMD-Xilinx FPGA families. The paper details the design of an INT8 multiplier using the proposed approach, presenting implementation results and accuracy assessments for the inference of benchmark deep learning models. The implementation results reveal significant savings of 53.6% in LUT utilization compared to the standard INT8 Xilinx multiplier. Accuracy measurements conducted on four popular deep learning benchmarks show an average accuracy degradation of 4.8% in post-training deployment and 0.7% after retraining. The source code for this work is available on GitHub(1).

关键词： approximate multiplier field-programmable gate array machine learning computing

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Development of plasma control system for divertor configuration on QUEST

Development of plasma control system for divertor configurat...

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27th Symposium on Fusion Technology (SOFT)

作者： Hasegawa, M. Nakamura, K. Zushi, H. Hanada, K. Fujisawa, A. Matsuoka, K. Mitarai, O. Idei, H. Nagashima, Y. Tokunaga, K. Kawasaki, S. Nakashima, H. Higashijima, A. Kyushu Univ Appl Mech Res Inst Kasuga Fukuoka 816 Japan Tokai Univ Toro Ku Kumamoto Japan

A plasma control system to sustain divertor configurations is developed on QUEST (Q-shu university experiment with steady-state spherical tokamak). Magnetic fluxes are numerically integrated at 100 kHz using FPGA (field-programmable gate array) modules and transferred to a main calculation loop at 4 kHz. With these signals, plasma shapes are identified in real time at 2 kHz under the assumption that the plasma current can be represented as one filament current. This calculation is done in another calculation loop in parallel by taking advantage of a multi-core processor of the plasma control system. The inside and outside plasma edge positions are controlled to their target positions using PID (proportional-integral-derivative) control loops. Whereas the outside edge position can not be controlled by the outer PF coil current, the inside edge position can be controlled by the inner PF coil current. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Plasma shape identification Real-time control Divertor configuration field-programmable gate array

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Hardware-Accelerated Index Construction for Semantic Web 17

Hardware-Accelerated Index Construction for Semantic Web

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17th International Conference on field-programmable Technology (FPT)

作者： Blochwitz, Christopher Wolff, Julian Berekovic, Mladen Heinrich, Dennis Groppe, Sven Joseph, Jan Moritz Pionteck, Thilo Univ Lubeck Inst Comp Engn D-23562 Lubeck Germany Univ Lubeck Inst Informat Syst D-23562 Lubeck Germany Otto von Guericke Univ Inst Informat Technol & Commun D-39106 Magdeburg Germany

ISBN: (纸本)9781728102139

In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardware engine for index construction are presented. We propose an FPGA-centric design, which we call Hardware-Triplestore. As part of the design, a scalable and parallel architecture for Triplestore construction is introduced. We propose a hybrid data structure consisting of three layers, one for every element of the semantic triple. The data structure is optimized for our hardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately from the rest of the database system and achieves an insertion rate of 1.24 million triples per second, which is 17 times faster than one of the fastest software Triplestore-RDF-3X-.

关键词： Triplestore RDF-3X Semantic Web Database Hardware field-programmable gate array

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Model Predictive Control Driven Transformer Coupled Parallel Hybrid Si IGBT/SiC MOSFET Converter 39

Model Predictive Control Driven Transformer Coupled Parallel...

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Applied Power Electronics Conference and Exposition (APEC)

作者： Li, Ning Finney, Stephen Judge, Paul D. Univ Edinburgh Inst Energy Syst Edinburgh Midlothian Scotland

ISBN: (纸本)9798350316643

This paper investigates the design of a Parallel Hybrid Converter topology for DC/AC applications connected using a three-winding transformer. The original Parallel Hybrid Converter (PHC) topology consists of a Silicon IGBT bridge and a partially rated Silicon Carbide MOSFET bridge with a shared DC bus. A common-mode inductor is needed in this topology to mitigate the circulating current between the two bridges. This paper introduces a novel variant of the PHC with a three-winding transformer that removes the requirement of the common-mode inductor. Component sizing optimisation for this topology is performed using a Non-Denominated Set Genetic Algorithm. A Long-Horizon Model predictive control method will be implemented into the FPGA real-time system, including the MOSFET bridge's current limit constraint in the cost functions. Experimental tests validate the performance of this topology and implementation of FPGA, with an IGBT bridge frequency about 1000 Hz and grid-side output current THD below 3% achieved.

关键词： Power Electronic Converter Partial Load Efficiency Silicon Carbide MOSFETs Three-Winding Transformer field-programmable gate array

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FPGA-based Reservoir Computing with Optimized Reservoir Node Architecture 23

FPGA-based Reservoir Computing with Optimized Reservoir Node...

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23rd International Symposium on Quality Electronic Design (ISQED)

作者： Lin, Chunxiao Liang, Yibin Yi, Yang Virginia Tech Bradley Dept Elect & Comp Engn Blacksburg VA USA

ISBN: (纸本)9781665494663

Updating the state of reservoir nodes is one of the essential operations of reservoir computing (RC), which highly affects the system's performance. In an echo state network (ESN), one of the primary types of RC, the process of state renewal can be divided into two stages: multiplication of the weight matrix with the input-state vector and applying a nonlinear activation function on the sum of products. The weight matrix is typically large and sparse, providing opportunities for optimizing the matrix multiplication;the choices of activation functions may also affect hardware resource utilization. This paper introduces an optimized reservoir node architecture for FPGA-based RC systems. Specifically, we adopt the bit-serial matrix multiplier and direct spatial implementation of the weight matrix to fully exploit the sparseness property. The canonical signed digit representation is also employed to further optimize the multiplier logic. Furthermore, a hyperbolic tangent activation function is designed and optimized to maintain the nonlinearity of the neural network without affecting its accuracy. Compared with existing hardware ESN designs, our reservoir node architecture significantly reduces resource utilization while maintaining comparable performance.

关键词： Reservoir computing field-programmable gate array echo state network architecture

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Development of an IP-cores Libraries as Part of the Design Flow of Integrated Circuits on FPGA

Development of an IP-cores Libraries as Part of the Design F...

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Khvatov, Vasilii M. Zheleznikov, Daniil A. Russian Acad Sci IPPM RAS Inst Design Problems Microelect Moscow Russia

ISBN: (纸本)9781665404761

IP-core is a block with a complex function that can be re-used in integrated circuits design. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed interconnects while soft IP-cores can be synthesized from logic elements and should be placed and routed. To use IP-cores in automated design flow of integrated circuits on FPGA it is necessary to develop IP-cores libraries that allow identifying blocks on every stage of flow. This article shows IP-core libraries types and forms used as a part of design flow developed by IPPM RAS for Russian FPGA. It describes challenges of libraries for logical synthesis development and automatic mapping on an existing basis. The paper presents libraries needed by CAD on every stage of physical design for clustering, placement and routing. Also, it considers soft and hard IP-cores libraries distinct features and methods of their formation taking into account the FPGA architecture.

关键词： IP-cores library field-programmable gate array FPGA Design Flow Integrated Circuit

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FPGA Implementation of Second-Order Difference Plot for Epileptic Seizure Detection in EEG Signals 12

FPGA Implementation of Second-Order Difference Plot for Epil...

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12 IEEE Int C Elect Energy Env Communications Computer Control

作者： Singh, Ardra Prince, A. Amalin Birla Inst Technol & Sci Pilani Elect & Elect Engn Dept KK Birla Goa Campus Pilani Goa India

ISBN: (纸本)9781467365406

field-programmable gate arrays (FPGAs) are being extensively used for a wide range of digital applications due to their flexibility and reprogrammability. This paper presents a FPGA implementation of the second -order difference plot (SODP) technique which can be used for the classification of ictal and seizure -free electroencephalogram (EEG) signals. Empirical mode decomposition (EMD) can break down an EEG signal into simple oscillatory modes called intrinsic mode functions (IMFs). The hardware design developed takes a sampled IMF of an EEG signal as input and generates its SODP while simultaneously calculating the 95 percent confidence ellipse area of the SODP. The ellipse area can be used as a parameter for detecting epileptic seizures in EEG signals. The digital circuit was designed in the Vivado integrated development environment (IDE) using Verilog hardware description language (HDL) and a Xilinx Artix-7 xc7a100tcsg324 FPGA was used to verify operation of the physical implementation. The hardware was tested on EEG data made publicly available by the University of Bonn and the results were found to be consistent with MATLAB simulations.

关键词： field-programmable gate array epileptic seizure electroencephalogram signal second-order difference plot 95% confidence ellipse area

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Architecture of IoT-based Collaborative Laboratory for Reconfigurable SoC: Review and Development 2

Architecture of IoT-based Collaborative Laboratory for Recon...

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IEEE 2nd German Education Conference (GECon)

作者： Al Amin, Rashed Wiese, Veit Rahman, Mohammad Musfiqur Jacobs, Sven Jaschke, Steffen Obermaisser, Roman Univ Siegen Inst Embedded Syst Siegen Germany Univ Siegen Comp Sci Educ Siegen Germany

ISBN: (纸本)9798350348132

Reconfigurable System-on-Chip (SoC) is a computing architecture that allows users to program and reprogram the hardware to perform different tasks, making it highly flexible and adaptable. Due to its potential to significantly accelerate various applications, reconfigurable SoC has become a subject of much research for academicians and industry. On the other hand, the classical practice of experimenting in the laboratory has been changing radically with the advanced utilization of computers, electronic devices, and the internet. As a result, it has given birth to a new concept of laboratory practice called Internet-of-Things (IoT) based collaborative simulation laboratory, which enables students to access and use the laboratory equipment at their convenience, enabling them to learn at their own pace and comfort. First, this paper reviewed the state of the art of reconfigurable SoC, specially field-programmable gate arrays (FPGAs) laboratory architecture. Then, it developed an IoT-based collaborative simulation laboratory for reconfigurable SoC, allowing multiple students to work together to solve laboratory tasks remotely. Furthermore, this laboratory architecture is for reconfigurable FPGAs, which can manage several tasks automatically, such as logic synthesis, logic simulation, and FPGA run from multiple FPGAs or SoC. In addition to its benefits, the capability to virtualize user input/output interfaces and remotely measure the design's response further enhances its advantages. However, this proposed laboratory architecture is essential not only for doing laboratory tasks remotely but also simplifies the existing teaching methods and helping evaluate student performance in the examination.

关键词： system-on-chip field-programmable gate array internet-of-things remote laboratory

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The Review of Cellular Automata Algorithms for Placement and Routing Problems

The Review of Cellular Automata Algorithms for Placement and...

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Zapletina, Mariya A. Zhukov, Denis, V RAS CAD Dept Inst Design Problems Microelect Zelenograd Russia

ISBN: (纸本)9781665404761

The paper proposes a review of the modern research experience of the cellular automata algorithms, models and methods to solve the problem of searching the shortest paths and the placement task for the logic elements within the design flow for FPGA. The classical and hybrid cellular automata models are considered. The particular attention is paid to the cellular automata with multi-agent semantics for the shortest path search algorithms. A detailed analysis of the model for solving the placement problem based on the systolic structure is given. The main difficulties and possible problems of the cellular automata models and algorithms for placement and routing stages of an FPGA design flow are highlighted and discussed.

关键词： cellular automata field-programmable gate array FPGA placement routing multi-agent shortest path search

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Radar Pulse on Pulse Identification Algorithm Hardware Acceleration Performance Analysis 11

Radar Pulse on Pulse Identification Algorithm Hardware Accel...

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IEEE 11th Annual Computing and Communication Workshop and Conference (CCWC)

作者： Juliano, Jordan Lin, Jaron Erdogan, Alex George, Kiran Calif State Univ Fullerton Comp Engn Fullerton CA 92634 USA

ISBN: (纸本)9781665414906

The performance in radar receiver signal processing is a critical factor in identifying radar pulses. The use of field-programmable gate arrays (FPGA) in hardware acceleration provides multiple advantages in radar signal processing. High-level synthesis (HLS) tools enable systems developed in high-level languages, such as C, flexibility in conversion to a register-transfer level (RTL) design. A direct HLS translation for an FPGA target may not always improve performance, and analysis is compelling in systems where speed and performance are crucial. System on a Chip (SoC) FPGAs includes a processing system (PS) and programmable logic (PL) architectures on a single device. The performance between high-level language designs executed on the PS and HLS adaption implemented on the PL can be directly analyzed. This paper presents the performance comparisons of a Python and HLS versions of a previous work radar pulse on pulse identification algorithm implemented on an SoC FPGA.

关键词： High-Level Synthesis field-programmable gate array Digital Signal Processing SoC Receivers

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