Software-defined radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modifiable software or firmware. This paper de...
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Software-defined radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modifiable software or firmware. This paper describes the coarse-grained reconfigurable array (CGRA) implementations of SDR architecture. This architecture is an extension of traditional SDR in complex adaptation strategies, such as highly reliable communications and efficient utilization of the resources and spectrum upgrade, through its internal states (performance) and hardware architecture. The proposed CGRA-based SDR implementation is based on dynamic partial reconfiguration methodology, which has the capability of reusing the same hardware module to handle different algorithms. This CGRA-based SDR provides greater flexibility and adds new abilities without additional cost. Initially, the SDR system was simulated in the Agilent SystemVue environment to analyze the error boundaries of the proposed SDR architecture. Then the SDR system was coded in the Verilog hardware description language and implemented on top of CGRAs such as the MOLEN, MORPHOSYS, and ADRES reconfigurable system-on-chip (SoC) architectures. These SoC architectures were installed within the Xilinx Virtex 5 field-programmable gate array to analyze the performance of SDR architectures in terms of area utilization, operational speed, power optimization, reconfiguration time, coprocessor execution time, preemption support, and relocation support of the system. The performance analysis indicates that the ADRES SoC architecture is suitable for dynamic partial reconfiguration and the MOLEN SoC architecture is more suitable for power, area, and speed requirements and low circuit complexity compared to other architectures.
This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical de...
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This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.
INS-GPS integration is a fundamental task used to enhance the accuracy of an inertial navigation system alone. However, its implementation complexity has been a challenge to most embedded systems. This paper proposes ...
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INS-GPS integration is a fundamental task used to enhance the accuracy of an inertial navigation system alone. However, its implementation complexity has been a challenge to most embedded systems. This paper proposes a low-cost FPGA-based INS-GPS integration system, which consists of a Kalman filter and a soft processor. Moreover, we also evaluate the navigation algorithm on a low-cost ARM processor. Processing times and localization accuracy are compared in both cases for single and double precision floating-point format. Experimental results show the advantages of the FPGA-based approach over the ARM-based approach. The proposed architecture can operate at 100 Hz and demonstrates the advantage of using FPGAs to design low-cost INS-GPS localization systems.
Clock and data recovery (CDR) is an essential part in high-speed telecommunication systems. The CDR is used to extract the clock and re-time the received data, which allows a synchronous operation to recover the trans...
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Clock and data recovery (CDR) is an essential part in high-speed telecommunication systems. The CDR is used to extract the clock and re-time the received data, which allows a synchronous operation to recover the transmitted signal. In optical access networks, electrical CDR or optical CDR implementations can be used. However, there are no clear guidelines or recommendations on which CDR implementation should be adopted for better performance. These missing clear recommendations are because the electrical CDR requires electronics design expertise whereas the optical CDR requires optical design expertise. Consequently, in this paper, an all-digital CDR, designed and implemented on the field-programmable gate array platform, and an optical CDR, developed by using fiber Bragg grating technology on the OptiSystem platform, are presented. Furthermore, the integration of these 2 CDR implementations with the optical access network is implemented, and their performance is evaluated for various transmission rates and communication distances. Finally, a comparative study in terms of the bit error rate between the all-digital CDR and the optical CDR is presented.
Integrated circuit implementations of new models of neural networks with scale-invariant properties are presented. The specifics of such models are necessary in analysis of discrete mappings containing fractional powe...
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Integrated circuit implementations of new models of neural networks with scale-invariant properties are presented. The specifics of such models are necessary in analysis of discrete mappings containing fractional power. We suggest an algorithm for increasing the power of a physical value by using a field-programmable gate array (FPGA). Comparisons between FPGA implementations and numerical results are demonstrated.
Steganography methods conceal covert messages inside communicated data. field-programmable gate array (FPGA) hardware implementation provides speed, flexibility and configurability. It is extremely difficult to compar...
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Steganography methods conceal covert messages inside communicated data. field-programmable gate array (FPGA) hardware implementation provides speed, flexibility and configurability. It is extremely difficult to compare published results from different platforms and technologies. The goal of our research work is to mitigate the dependency by examining implementations from multiple FPGA platforms. The research studies the implementations of 12 spatial steganography methods using Altera and Xilinx FPGAs. The methods include mix-bit LSB, least significant bit (LSB), random LSB and texture-based algorithms. The objective of the research is to develop platform-independent resources, timing, power and energy models;to empower future steganography research. Further, the article evaluates steganography methods using typical performance metrics as well as a novel performance metric. The results suggest that the mix-bit methods exhibit good performance across most of the metrics. However, when image quality is a concern, the two-bit LSB is the front runner.
Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion t...
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Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion ( SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient field-programmable gate array ( FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38x performance improvement over the original MATLAB implementation and a 1.33x performance improvement over the hardware implementation using the Xilinx System Generator tool.
The paper presents a field-programmable gate array (FPGA)-based fast processing system with 12-channel high-resolution (24 bits) front-end for ECG signal processing. The implemented high-resolution data conversion mak...
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The paper presents a field-programmable gate array (FPGA)-based fast processing system with 12-channel high-resolution (24 bits) front-end for ECG signal processing. The implemented high-resolution data conversion makes the system suitable for recording of late potentials of the QRS complex in patients prone to sustained ventricular tachycardia. The system accepts ECG signals through 12 channels and then filtered to minimize baseline wander and power-line interference. The filter outputs are connected to 12 delta-sigma ADCs. The whole ADCs work synchronously at 8 kHz sampling frequency, and their output data are transferred to an FPGA that computes online on the digitized sample values in real time and ascertains whether the patient under study suffers from ventricular tachycardia or not. In order to ascertain the QRS complex accurately in the noisy ECG signal, fuzzy entropy of the sample values has been computed and provided as an input to inverse multiquadratic radial basis function neural network. Using the standard CSE ECG database, the algorithm performed highly effectively. The performance of the algorithm in respect of QRS detection with sensitivity of 99.83 % and accuracy of 99.7 % is achieved when tested using single-channel ECG with entropy criteria. The performance of the QRS detection system has been compared and found to be better than most of the QRS detection systems available in the literature. Using the system, 200 patients have been diagnosed with an accuracy of 99 %.
A time-to-digital converter-based system, to be used for most subdetectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital trigger and data acquisition system in wh...
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A time-to-digital converter-based system, to be used for most subdetectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital trigger and data acquisition system in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four high-performance time-to-digital converters (HPTDCs), measure hit times from subdetectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors, and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB developed by the Pisa NA62 group are extensively discussed and performance data are presented in order to show its compliance with the experiment requirements.
The dc current-stress tolerance of the ON-state Cu atom switch is evaluated at elevated temperature. It is revealed that the reset-direction current stress causes time-dependent failures, which originate from the E-fi...
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The dc current-stress tolerance of the ON-state Cu atom switch is evaluated at elevated temperature. It is revealed that the reset-direction current stress causes time-dependent failures, which originate from the E-field-driven diffusion of Cu in the conducting bridge. A new empirical lifetime estimation model, including the Joule heating effect, gives an allowable maximum current per atom switch of I-max = 115 mu A, which is large enough to satisfy the requirements for signal routing under currents that are average (18 mu A) and peak (63 mu A) in the reconfigurable switch block operated at 500 MHz at 125 degrees C.
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