In this paper we propose a design based on a genetic algorithm to evolve the logic circuit of a defined input function, in which we aim to minimize the total number of gates used. Our design is outlined and briefly di...
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ISBN:
(纸本)0780366468
In this paper we propose a design based on a genetic algorithm to evolve the logic circuit of a defined input function, in which we aim to minimize the total number of gates used. Our design is outlined and briefly discussed, while our preliminary results are presented and analyzed.
This paper presents a pair of fieldprogrammablegatearray (FPGA) test chips optimized for subthreshold operation to maximize energy efficiency. Both chips were fabricated in the IBM 0.18 mu m silicon-on-insulator (S...
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ISBN:
(纸本)9781467315876
This paper presents a pair of fieldprogrammablegatearray (FPGA) test chips optimized for subthreshold operation to maximize energy efficiency. Both chips were fabricated in the IBM 0.18 mu m silicon-on-insulator (SOI) process using the same FPGA architecture;one making use of conventional static CMOS multiplexers and one using dynamic threshold MOS (DTMOS) multiplexers. Reliable subthreshold operation is achieved for both test chips by replacing conventional SRAM with variation-tolerant interruptible latches. For the chip with conventional multiplexers, testing across eleven dice showed an average minimum operating voltage of 300 mV. A 43X reduction in power delay product (PDP) was seen compared to 1.5V operation. For the DTMOS chip, testing across four dice showed an average minimum operating voltage of 260 mV. The test results show that the DTMOS chip is more reliable at sub-300 mV, consistent with simulations. Minimum energy analysis of both test chips suggests that the minimum energy point for the FPGA occurs at subthreshold voltages.
This paper presents a high-speed floating-point analog-to-digital converter in the framework of deterministic signal acquisition systems. The proposed circuit allows quantization of large dynamics signals, while keepi...
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ISBN:
(纸本)0780372182
This paper presents a high-speed floating-point analog-to-digital converter in the framework of deterministic signal acquisition systems. The proposed circuit allows quantization of large dynamics signals, while keeping a low relative error. FP-ADC precision characteristics are analyzed In the context of exponential decay signals acquisition.
Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this...
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ISBN:
(纸本)9798350396249
Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this work, we aim at a fair comparison of several languages (and tools), including Verilog (our baseline), Chisel, Bluespec SystemVerilog (Bluespec Compiler), DSLX (XLS), MaxJ (MaxCompiler), and C (Bambu and Vivado HLS). Our analysis has been carried out using a representative example of 8x8 inverse discrete cosine transform (IDCT), a widely used algorithm engaged in JPEG and MPEG decoders. The metrics under consideration include: (a) the degree of automation (how much less code is required compared to Verilog), (b) the controllability (possibility to achieve given design characteristics, namely a given ratio of the performance and area), and (c) the flexibility (ease of design modifications to achieve certain characteristics). Rather than focusing on computational kernels only, we use AXI-Stream wrappers for the synthesized implementations, which allows adequately evaluating characteristics of the designs when they are used as parts of real systems. Our study shows clear examples of what impact specific optimizations (tool settings and source code modifications) have on the overall system performance and area. It emphasizes how important is to be able to control the balance between the communication interface utilization and the computational kernel performance and delivers clear guidelines for the next generation tools for designing FPGA-accelerator-based systems.
This paper considers one of the methods for controlling the current source inverter, which uses previously generated control signals for the voltage source inverter. Describes the instructional method for converting t...
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ISBN:
(纸本)9781467367196
This paper considers one of the methods for controlling the current source inverter, which uses previously generated control signals for the voltage source inverter. Describes the instructional method for converting these signals with minimization of switching losses. Analysis results are verified with simulation modeling of control systems in the software PowerSIM, as well as experimental investigations of microprocessor control system based on field-programmable gate array.
In this paper, we study FPGA implementation of a novel receiver diversity combining technique, RMSGC for wireless transmission over fading channels in SIMO systems. Prior published results using ML-detected RMSGC dive...
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ISBN:
(纸本)9781424412358
In this paper, we study FPGA implementation of a novel receiver diversity combining technique, RMSGC for wireless transmission over fading channels in SIMO systems. Prior published results using ML-detected RMSGC diversity signal driven by BPSK showed superior bit error rate performance to classical diversity combining schemes. RMSGC was shown to be near-optimal in the sense that it was very close to that of the theoretically optimal MRC. Since MRC requires estimation of the channel coefficients, it is complicated and expensive, and it is not practical for non-coherent modulation and differentially coherent modulation. RMSGC, on the other hand, is a more attractive and simpler scheme since it does not require knowledge of the channel information states. The main drawback of RMSGC is that it is a non-linear technique, thus successful FPGA implementation of it using pipeline techniques is needed as a wireless communication test-bed for practical real-life situations. Simulation results showed that the hardware implementation was efficient both in terms of speed and area.
Functional verification is an important aspect of electronic design automation. Traditionally, simulation at the register transfer-level has been the mainstream functional verification approach. Formal verification an...
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ISBN:
(纸本)9781450356268
Functional verification is an important aspect of electronic design automation. Traditionally, simulation at the register transfer-level has been the mainstream functional verification approach. Formal verification and various static analysis checkers have been used to complement specific corners of logic simulation. However, as the size of IC designs grow exponentially, all the above approaches fail to scale with the design growth. In recent years, logic emulation have gained popularity in functional verification, partly due to their performance and scalability benefits. There are two main approaches to logic emulation: ASIC and commercial field-programmable gate array (FPGA). In this paper, we focus on commercial FPGA based logic emulation and present various challenging problems in this area for the academic community.
field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation function...
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ISBN:
(纸本)9798350359114
field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has hardcoded the combination of linear maps and nonlinear activations inside FPGA lookup tables (LUTs). Our work is motivated by the idea that the LUTs in an FPGA can be used to implement a much greater variety of functions than this. In this paper, we propose a novel approach to training neural networks for FPGA deployment using multivariate polynomials as the basic building block. Our method takes advantage of the flexibility offered by the soft logic, hiding the polynomial evaluation inside the LUTs with minimal overhead. We show that by using polynomial building blocks, we can achieve the same accuracy using considerably fewer layers of soft logic than by using linear functions, leading to significant latency and area improvements. We demonstrate the effectiveness of this approach in three tasks: network intrusion detection, jet identification at the CERN Large Hadron Collider, and handwritten digit recognition using the MNIST dataset.
In this work a review of the more outstanding contributions, carried out in the automatic control context, that deal with the trajectory tracking task in autonomous wheeled mobile robots (WMR) by using an embedded sys...
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ISBN:
(纸本)9781467383295
In this work a review of the more outstanding contributions, carried out in the automatic control context, that deal with the trajectory tracking task in autonomous wheeled mobile robots (WMR) by using an embedded system is presented. In this direction, with the intention of describing an embedded system, some definitions of such a system and also the parts integrating it are introduced. The contributions related to the trajectory tracking task in WMR are grouped according to the used hardware, namely, microcontroller, field-programmable gate array, and digital signal processor. Additionally, works that use an embedded system in the implementation of the trajectory tracking task for a WMR, but they do not give importance to such a system are included. Moreover, studies using personal computers and laptops to execute some control problems associated with WMR are considered. In general, this paper points the works dealing with the use of embedded systems in WMR, identifying a wide variety of embedded systems models.
A simple and improved digital timing method has been developed for positron emission tomography (PET). The so-called initial rise interpolation method is based on an important characteristic of gamma signal: a properl...
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ISBN:
(纸本)9781424439614
A simple and improved digital timing method has been developed for positron emission tomography (PET). The so-called initial rise interpolation method is based on an important characteristic of gamma signal: a properly pre-amplified and sampled gamma signal pulse can be characterized to arrive with an initial rise from baseline and then to go up with a maximum rise. Pulse arrival time is obtained by calculating the intersection of the initial rise line with the baseline for each gamma signal pulse. In this study, a FPGA-based data acquisition (DAQ) card was used for data acquisition and processing. We measured coincidence timing resolution of two types (fast and slow) of recently developed 3 mm x 3 mm Geiger mode avalanche photodiodes (GAPDs) using 3 different digital timing methods: initial rise interpolation (IRO, digital CFD and maximum rise interpolation (MRI). Furthermore, simulation has been performed to evaluate effects of pulse rise time, pulse amplitude and front-end noise level on timing resolution estimated by the three digital timing methods. Measured results show that, IRI method provided the best timing resolution for both types of GAPDs: 0.7 ns FWHM for fast GAPD and 1.5 ns for slow GAPD (digital CFD: 1.5 ns and 2.2 ns;MRI: 1.8 ns and 2.7 ns). In accordance with measured results, simulation results also show that IRI method provided the best timing resolution. Based on these experimental results, we concluded that the developed simple and improved digital timing method is reliable and useful for the development of high performance PET.
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