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检索条件"主题词=Field-programmable gate array"

共 571 条记录，以下是411-420 订阅

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The design of an evolvable coprocessor environment

The design of an evolvable coprocessor environment

引用

18th IEEE Instrumentation and Measurement Technology Conference (IMTC/2001)

作者： Abielmona, R Groza, V Univ Ottawa Sch Informat Technol Engn Ottawa ON K1N 6N5 Canada

In this paper we propose a design based on a genetic algorithm to evolve the logic circuit of a defined input function, in which we aim to minimize the total number of gates used. Our design is outlined and briefly di... 详细信息

ISBN: (纸本)0780366468

关键词： genetic algorithm field-programmable gate array evolvable hardware

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Characterization of a Single-Supply Subthreshold FPGA

Characterization of a Single-Supply Subthreshold FPGA

引用

IEEE Subthreshold Microelectronics Conference (SubVT)

作者： Grossmann, Peter Leeser, Miriam Onabajo, Marvin Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781467315876

This paper presents a pair of field programmable gate array (FPGA) test chips optimized for subthreshold operation to maximize energy efficiency. Both chips were fabricated in the IBM 0.18 mu m silicon-on-insulator (SOI) process using the same FPGA architecture;one making use of conventional static CMOS multiplexers and one using dynamic threshold MOS (DTMOS) multiplexers. Reliable subthreshold operation is achieved for both test chips by replacing conventional SRAM with variation-tolerant interruptible latches. For the chip with conventional multiplexers, testing across eleven dice showed an average minimum operating voltage of 300 mV. A 43X reduction in power delay product (PDP) was seen compared to 1.5V operation. For the DTMOS chip, testing across four dice showed an average minimum operating voltage of 260 mV. The test results show that the DTMOS chip is more reliable at sub-300 mV, consistent with simulations. Minimum energy analysis of both test chips suggests that the minimum energy point for the FPGA occurs at subthreshold voltages.

关键词： field-programmable gate array subthreshold FPGA minimum energy operation variation-aware design low-power design power-delay product

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Floating-point ADC optimized for acquisition of deterministic signals

Floating-point ADC optimized for acquisition of deterministi...

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19th IEEE Instrumentation and Measurement Technology Conference (IMTC/2002)

作者： Groza, V Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)0780372182

This paper presents a high-speed floating-point analog-to-digital converter in the framework of deterministic signal acquisition systems. The proposed circuit allows quantization of large dynamics signals, while keeping a low relative error. FP-ADC precision characteristics are analyzed In the context of exponential decay signals acquisition.

关键词： floating-point analog-to-digital converter field-programmable gate array error analysis

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High-Level Synthesis versus Hardware Construction

High-Level Synthesis versus Hardware Construction

引用

Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Kamkin, Alexander Chupilko, Mikhail Lebedev, Mikhail Smolov, Sergey Gaydadjiev, Georgi RAS ISP Moscow Russia Plekhanov RUE Moscow Russia HSE MSU MIPT Moscow Russia Univ Groningen Groningen Netherlands

ISBN: (纸本)9798350396249

Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this work, we aim at a fair comparison of several languages (and tools), including Verilog (our baseline), Chisel, Bluespec SystemVerilog (Bluespec Compiler), DSLX (XLS), MaxJ (MaxCompiler), and C (Bambu and Vivado HLS). Our analysis has been carried out using a representative example of 8x8 inverse discrete cosine transform (IDCT), a widely used algorithm engaged in JPEG and MPEG decoders. The metrics under consideration include: (a) the degree of automation (how much less code is required compared to Verilog), (b) the controllability (possibility to achieve given design characteristics, namely a given ratio of the performance and area), and (c) the flexibility (ease of design modifications to achieve certain characteristics). Rather than focusing on computational kernels only, we use AXI-Stream wrappers for the synthesized implementations, which allows adequately evaluating characteristics of the designs when they are used as parts of real systems. Our study shows clear examples of what impact specific optimizations (tool settings and source code modifications) have on the overall system performance and area. It emphasizes how important is to be able to control the balance between the communication interface utilization and the computational kernel performance and delivers clear guidelines for the next generation tools for designing FPGA-accelerator-based systems.

关键词： electronic design automation application-specific computing hardware construction high-level synthesis field-programmable gate array inverse discrete cosine transform

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FPGA IMPLEMENTATION OF A NOVEL RECEIVER DIVERSITY COMBINING TECHNIQUE FOR WIRELESS SIMO SYSTEMS

FPGA IMPLEMENTATION OF A NOVEL RECEIVER DIVERSITY COMBINING ...

引用

IEEE International Conference on Signal Processing and Communications

作者： Ayoubi, R. Dubois, J. P. Abdul-Latif, O. Univ Balamand Koura North Lebanon Univ Bath Bath BA2 7AY Avon England

ISBN: (纸本)9781424412358

In this paper, we study FPGA implementation of a novel receiver diversity combining technique, RMSGC for wireless transmission over fading channels in SIMO systems. Prior published results using ML-detected RMSGC diversity signal driven by BPSK showed superior bit error rate performance to classical diversity combining schemes. RMSGC was shown to be near-optimal in the sense that it was very close to that of the theoretically optimal MRC. Since MRC requires estimation of the channel coefficients, it is complicated and expensive, and it is not practical for non-coherent modulation and differentially coherent modulation. RMSGC, on the other hand, is a more attractive and simpler scheme since it does not require knowledge of the channel information states. The main drawback of RMSGC is that it is a non-linear technique, thus successful FPGA implementation of it using pipeline techniques is needed as a wireless communication test-bed for practical real-life situations. Simulation results showed that the hardware implementation was efficient both in terms of speed and area.

关键词： field-programmable gate array maximal-ratio combining multiple-input multiple-output channels pipelining technique root-mean-square gain combining

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The Conversion Algorithm of Voltage Source Inverter Control Signals for Operating Current Source Inverter 16

The Conversion Algorithm of Voltage Source Inverter Control ...

引用

16th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices

作者： Volkov, Alexander G. Makarov, Denis V. Zharkov, Maksim A. Balagurov, Maxim V. Novosibirsk State Tech Univ Novosibirsk Russia

ISBN: (纸本)9781467367196

This paper considers one of the methods for controlling the current source inverter, which uses previously generated control signals for the voltage source inverter. Describes the instructional method for converting these signals with minimization of switching losses. Analysis results are verified with simulation modeling of control systems in the software PowerSIM, as well as experimental investigations of microprocessor control system based on field-programmable gate array.

关键词： currents source inverter voltage source inverter control algorithm field-programmable gate array

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Challenges in Large FPGA-based Logic Emulation Systems 18

Challenges in Large FPGA-based Logic Emulation Systems

引用

ACM International Symposium on Physical Design (ISPD)

作者： Hung, William N. N. Sun, Richard Synopsys Mountain View CA 94043 USA

ISBN: (纸本)9781450356268

Functional verification is an important aspect of electronic design automation. Traditionally, simulation at the register transfer-level has been the mainstream functional verification approach. Formal verification and various static analysis checkers have been used to complement specific corners of logic simulation. However, as the size of IC designs grow exponentially, all the above approaches fail to scale with the design growth. In recent years, logic emulation have gained popularity in functional verification, partly due to their performance and scalability benefits. There are two main approaches to logic emulation: ASIC and commercial field-programmable gate array (FPGA). In this paper, we focus on commercial FPGA based logic emulation and present various challenging problems in this area for the academic community.

关键词： Logic emulation field-programmable gate array

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PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference 22

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latenc...

引用

22nd International Conference on field programmable Technology (ICFPT)

作者： Andronic, Marta Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9798350359114

field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has hardcoded the combination of linear maps and nonlinear activations inside FPGA lookup tables (LUTs). Our work is motivated by the idea that the LUTs in an FPGA can be used to implement a much greater variety of functions than this. In this paper, we propose a novel approach to training neural networks for FPGA deployment using multivariate polynomials as the basic building block. Our method takes advantage of the flexibility offered by the soft logic, hiding the polynomial evaluation inside the LUTs with minimal overhead. We show that by using polynomial building blocks, we can achieve the same accuracy using considerably fewer layers of soft logic than by using linear functions, leading to significant latency and area improvements. We demonstrate the effectiveness of this approach in three tasks: network intrusion detection, jet identification at the CERN Large Hadron Collider, and handwritten digit recognition using the MNIST dataset.

关键词： deep learning inference field-programmable gate array hardware accelerator LUT-based neural networks soft logic

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A Review of Embedded Systems Used in WMR for the Trajectory Tracking Task

A Review of Embedded Systems Used in WMR for the Trajectory ...

引用

IEEE International Conference on Mechatronics, Electronics and Automotive Engineering (ICMEAE)

作者： Marquez-Sanchez, C. Silva-Ortigoza, R. Antonio-Cruz, M. Sosa-Cervantes, C. Y. Hernandez-Guzman, V. M. Inst Politecn Nacl CIDETEC Area Mecatron Unidad Profes Adolfo Lopez Mateos Mexico City 07700 DF Mexico Univ Autonoma Queretaro Fac Ingn Queretaro 76150 Qro Mexico

ISBN: (纸本)9781467383295

In this work a review of the more outstanding contributions, carried out in the automatic control context, that deal with the trajectory tracking task in autonomous wheeled mobile robots (WMR) by using an embedded system is presented. In this direction, with the intention of describing an embedded system, some definitions of such a system and also the parts integrating it are introduced. The contributions related to the trajectory tracking task in WMR are grouped according to the used hardware, namely, microcontroller, field-programmable gate array, and digital signal processor. Additionally, works that use an embedded system in the implementation of the trajectory tracking task for a WMR, but they do not give importance to such a system are included. Moreover, studies using personal computers and laptops to execute some control problems associated with WMR are considered. In general, this paper points the works dealing with the use of embedded systems in WMR, identifying a wide variety of embedded systems models.

关键词： Robotics Mechatronics Wheeled Mobile Robots Trajectory Tracking Task Embedded Systems Microcontroller field-programmable gate array Digital Signal Processor

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Development flow for FPGA-based scalable reconfigurable systems

Development flow for FPGA-based scalable reconfigurable syst...

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16th Euromicro Conference on Digital System Design (DSD)

作者： Caba, Julian Dondo, Julio D. Rincon, Fernando Barba, Jesus Lopez, Juan C. Univ Castilla La Mancha Dept Technol & Informat Syst E-13071 Ciudad Real Spain

ISBN: (纸本)9780769550749

Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, for instance we can change a part of the initial functionality after its deployment, where a complete configuration is not needed, and the total area required is reduced. However, the design of partially reconfigurable systems has been a complex task yet. This work try to facilitate the design process and proposes a new development flow, which reduces mistakes during first stages of the design and makes the building of partial reconfiguration projects easier. In addition, we provide a dedicated hardware component, which manages bitstreams and dynamic areas. This component speed up the reconfiguration time, accomplishing a speed about 180MB/s.

关键词： Dynamic Partial Reconfiguration Design Flow field-programmable gate array

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