This paper shows the results of the research aimed to find most efficient method of computation residue of dividing multi digit numbers by numbers of standard digit capacity. It is shown that application of the distri...
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ISBN:
(纸本)9781479971039
This paper shows the results of the research aimed to find most efficient method of computation residue of dividing multi digit numbers by numbers of standard digit capacity. It is shown that application of the distributed arithmetic allows processing multi digit numbers (more than 64-bit long) of any length by using only hardware resources of field-programmable gate array. It appears that there is a relation between value of partition parameter B and time for finding residue of division.
Passwords are a common way of securing systems and applications from unauthorized access. However, passwords can be vulnerable to attackers who try to crack them by using random guesses, common patterns (e.g., passwor...
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The incorporation of real-time Hardware-In-the-Loop (HIL) simulators has become one of the pillars of the power electronics control design cycle. This integration is necessary to verify the effectiveness of controller...
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Over the last several years, the Department of Defense has focused on conserving energy in order to enhance its combat capabilities. Renewable energy technologies, such as wind, solar, biomass, and others, have been e...
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Over the last several years, the Department of Defense has focused on conserving energy in order to enhance its combat capabilities. Renewable energy technologies, such as wind, solar, biomass, and others, have been explored so that the military can reduce its reliance on fossil fuels and improve its operational range. One of the components to this effort is solar photovoltaic (PV) technology. The purpose of this thesis is to demonstrate the importance of using a maximum power point tracking (MPPT) algorithm to ensure that a PV system provides the most energy possible. Moreover, two different MPPT algorithms are presented in this thesis. An interleaved boost converter controls the flow of power to a load and a 24-volt source. Also, it regulates the PV panel's voltage and current so that the panel may operate at its maximum power point. A complete model of the solar panel, boost converter, and control algorithms was created in Simulink in order to validate the system in simulation. The control algorithms were implemented using a field-programmable gate array so that the actual system could be tested and compared against the simulation. Experimental measurements validate the model and demonstrate that the MPPT algorithms perform as expected.
Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Deco...
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Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on field-programmable gate array (FPGA) are usually power- and area-hungry, but provide flexibility compared with application-specific integrated circuit implementations. With the penetration of mobile devices in the electronics industry the power considerations have become increasingly important. The power consumption of a digit-online decoder depends on various factors, like input log-likelihood ratio (LLR) bit precision, signal-to-noise ratio (SNR) and maximum number of *** design is implemented on an Altera Stratix IV GX EP4SGX230 FPGA, which comes on an Altera DE4 Development and Education Board. In this work, both parallel and digit-online block LDPC decoder implementations on FPGAs for WiMAX 576-bit, rate-3/4 codes are studied, and power measurements from the DE4 board are reported. Various components of the system include a random-data generator, WiMAX Encoder, shift-out register, additive white Gaussian noise (AWGN) generator, channel LLR buffer, WiMAX Decoder and bit-error rate (BER) Calculator. The random-data generator outputs pseudo-random bit patterns through an implemented linear-feedback shift register (LFSR). Digit-online decoders with input LLR precisions ranging from 6 to 13 bits and parallel decoders with input LLR precisions ranging from 3 to 6 bits are synthesized in a Stratix IV FPGA. The digit-online decoders can be clocked at higher frequency for higher LLR precisions. A digit-online decoder can be used to decode two frames simultaneously in frame-interlaced mode. For the 6-bit i
A software defined radio is a much more flexible platform than traditional, hardware implemented radios. By implementing radio functions in software, and putting those functions on a fieldprogrammablegatearray (FPG...
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A software defined radio is a much more flexible platform than traditional, hardware implemented radios. By implementing radio functions in software, and putting those functions on a fieldprogrammablegatearray (FPGA) chip, users will have the ability to download mission specific radio capabilities. This thesis examines a fundamental piece of the receiver, the Phase-Lock Loop (PLL), simulates a software PLL, and investigates the effects of fixed-point versus floating point mathematics required for an FPGA based PLL. With a fixed-point PLL simulator, figures of merit such as lock-time, lock range, and pull-in range are determined for typical signal-to-noise ratio (SNR) levels.
Regarding the high performance and reconfigurability of fieldprogrammablegate Ar- rays (FPGAs), many recent software defined radio (SDR) systems are currently being designed and developed on them. On the other hand,...
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Regarding the high performance and reconfigurability of fieldprogrammablegate Ar- rays (FPGAs), many recent software defined radio (SDR) systems are currently being designed and developed on them. On the other hand, a wide variety of applications in communication systems benefits from Phase-Shift Keying (PSK) modulation. There- fore, with respect to practical constraints and limitations, design and implementation of a robust and efficient FPGA-based structure for PSK modulation is an attractive subject of study. In practice, there is an unavoidable oscillator frequency difference between the transmit- ter and receiver which poses many challenges for designers. This frequency offset makes carrier recovery and time synchronization as two essential functions of every receiver. The possible solution lies in the closed loop control techniques. In other words, without feedback-based controllers, acceptable performance in a digital radio link is unachievable. The Costas Loop is one of the most effective methods for carrier recovery and its advantage over other methods is that the error signal in the feedback loop is twice as accurate. The Gardner time synchronization method is also introduced as a closed loop clock and data recovery technique and, regarding to its performance, is a potential candidate to be implemented on FPGA-based platforms. The main body of this thesis work is related to the realization aspects of these methods on FPGA. The thesis spans from the design and implementation of a baseband digital transceiver to connecting it to a radio frequency device, forming a Binary/Quadrature PSK modem. The introduced platform is developed on National Instruments Universal Software Radio Peripheral (NI USRP) equipped with a Xilinx Kintex 7 FPGA. Many case studies were conducted to evaluate the performance of similar systems con- sidering Signal to Noise Ratio (SNR). In this study, in addition to SNR, the effective- ness of the implemented transceiver has been evaluat
学位级别： M.S.E., Master of Science in Engineering/Education
This thesis first aims to understand how a part of the computed tomography (CT) algorithm called “forward projector” (FP) works and how it can be accelerated at a hardware level. Two methods of FP are defined and st...
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This thesis first aims to understand how a part of the computed tomography (CT) algorithm called “forward projector” (FP) works and how it can be accelerated at a hardware level. Two methods of FP are defined and studied: pixel-driven and ray-driven. Both methods fundamentally use the property of line integral and Bresenham’s algorithm. As the result of the study of the two FP methods, the ray-driven algorithm implemented in C++ performed 35% faster than the pixe-driven algorithm implemented in Python. This thesis implements the ray-driven forward projector algorithm using field-programmable gate array (FPGA), making use of hardware-acceleration techniques. The result shows that the FPGA implementation had a comparable speed advantage compared to the implementation on the personal computer (PC). Even though the FPGA used was outdated and budget-oriented, the chip was able to perform 58% of the performance of a more expensive, modern, and performance-oriented PC. Also, the FPGA implementation performed better in power consumption compared to the PC. Methodologies included the state machine, random access memory (RAM), and universal asynchronous receiver-transmitter (UART). By using the results in this thesis, a CT scanner can be designed to be less expensive, more efficient, faster, and use less power.
Tato bakalářská práce popisuje vývoj aplikace na platformě FITkit. Vývoj na zmíněné platformě obnáší vývoj konfigurace programovatelného hradlového pole (...
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Tato bakalářská práce popisuje vývoj aplikace na platformě FITkit. Vývoj na zmíněné platformě obnáší vývoj konfigurace programovatelného hradlového pole (FPGA) od společnosti Xilinx a vývoj programu pro mikrokontrolér od společnosti Texas Instruments. Aplikace má za úkol demonstrovat synchronizaci grafické aplikace běžící na dvou FITkitech současně. Komunikace mezi zařízeními probíhá přes sériovou linku.
The reliability of gyrotron operation is significantly decreased approaching the individual maximum output power of the tube due to loss of the nominal operating mode. For the first time, this paper proposes an algori...
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The reliability of gyrotron operation is significantly decreased approaching the individual maximum output power of the tube due to loss of the nominal operating mode. For the first time, this paper proposes an algorithm for an automated mode recovery (MORE) for gyrotrons exploiting the hysteretic gyrotron behaviour. The algorithm has been implemented in a field-programmable gate array (FPGA) controlling the acceleration voltage and is able to recover the nominal operating mode within <1 ms after a mode switch to the competing satellite mode. This allows the gyrotron to be operated closer to its stability limits with extended pulse lengths at potentially higher output power. Dedicated experiments to test MORE were conducted at Wendelstein 7-X (W7-X) with two gyrotrons using a beam dump. The nominal mode could be successfully recovered in 99% of 3755 modeloss events during 128 shots up to 20 s. MORE was operational for nine out of ten gyrotrons during the last experimental campaign OP1.2b of W7-X. The overall success rate during W7-X OP1.2b was 91% counting 464 modeloss events in 131 shots performed with seven gyrotrons. Using the mode losses in the working point plane, the cutoff region for the nominal working mode was identified, defining a minimum cathode current for a given acceleration voltage. The total achievable output power of the W7-X ECRH plant could be increased by at least 500 kW for the same pulse length using MORE, assuming a conservative increase of at least 50 kW per gyrotron. Comparing the output power for the same achievable pulse length and reliability level, the output power increase per gyrotron is likely in the order of 100 kW. Since MORE exploits the hysteretic gyrotron behaviour, it could be applied to other gyrotrons of already existing or future ECRH facilities of fusion experiments, like ITER.
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