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Improvement in Voltage Conversion Ratio of Ultrahigh Step-Down Converter

ENERGIES 2019年第20期12卷 3896-3896页

作者： Hwu, Kuo-Ing Jiang, Wen-Zhuang Tu, Hsiang-Hao Natl Taipei Univ Technol Dept Elect Engn 1Sec 3Zhongxiao E Rd Taipei 10608 Taiwan Chicony Power Technol Co Ltd New Taipei 21458 Taiwan Delta Elect Inc Taipei 11466 Taiwan

A modified step-down converter is presented herein, which is mainly based on one coupled inductor and several energy-transferring capacitors to improve the voltage conversion ratio as well as to reduce the switch voltage stress. In addition, the portion of the leakage inductance energy can be recycled to the input via the active clamp circuit during the turn-off period and the switches have zero-voltage switching (ZVS) during the turn-on transient. In this paper, the basic operating principles of the proposed converter are firstly described and analyzed, and its effectiveness is finally demonstrated by experiment based on a prototype with input voltage of 60 V, output voltage of 3.3 V and rated output power of 33 W.

关键词： active clamp circuit coupled inductor ultrahigh step-down converter field-programmable gate array zero-voltage switching voltage conversion ratio

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An FPGA Hardware-in-the-Loop Approach for Comprehensive Analysis and Development of Grid-Connected VSI System

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ENERGIES 2023年第2期16卷 759页

作者： Singh, Vijay Kumar Tripathi, Ravi Nath Rajiv Gandhi Inst Petr Technol Dept Elect Engn Jais 229305 Uttar Pradesh India Kyoto Univ Adv Sci Nagamori Actuator Res Ctr Kyoto 6158577 Japan

Power electronic converters are used for an efficient and controlled conversion of power generated from renewable energy sources and can interface generated power to the grid. Among available power converters, voltage source inverters (VSIs) have been widely employed for grid-connected applications due to better controllability with higher efficiency. Although various conventional, as well as modern control techniques, have been developed for grid connected VSI system, there is a need to select suitable control technique based on application and control requirements. Hardware-in-the-loop (HIL) is considered as a realistic approach for the development of system and control due to the inclusion of an actual hardware system. In this paper, a HIL approach is adopted for the comprehensive analysis and development of a grid connected VSI system using a field programmable gate array (FPGA). The control techniques must deal with trade-off, based on the features and limitations. Therefore, a grid-connected VSI system is developed considering employment of two different conventional control techniques: hysteresis current control (HCC) and PI-based space vector modulation (PI-SVM), as well as finite state model predictive control (FS-MPC) as a modern control technique for investigation considering different parameters. All three control systems are developed through a digital simulator of Xilinx that is integrated with MATLAB-Simulink, while considering an FPGA based system development and testing through FPGA HIL co-simulation methodology.

关键词： field-programmable gate array finite state model predictive control grid-connected system hardware-in-the-loop hysteresis current control space vector modulation voltage source inverter

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High-performance computer system dedicated to ray-wavefront conversion technique aimed to display holograms in real-time

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OPTICAL ENGINEERING 2023年第8期62卷 085102-085102页

作者： Maruyama, Tatsuya Ichihashi, Yasuyuki Hoshi, Ikuo Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Chiba Univ Grad Sch Engn Chiba Japan Natl Inst Informat & Commun Technol Radio Res Inst Koganei Japan

Holography is the ultimate three-dimensional (3D) imaging technology, and research is actively being conducted on generating at high-speed holograms with enormous amounts of information and improving image quality. Because computer holography is based on wave optics algorithms, reconstructing the texture of 3D images is difficult. On the other hand, in principle, reconstructing texture in integral photography based on geometric optics is easy and the method is well established. We developed a high-performance special-purpose computer, called holographic reconstruction for ultra-realistic imaging, dedicated to the ray-wavefront conversion method. The design and implementation of the circuit for the hologram generation were performed using field-programmable gate array technology. Parallelization was performed at each step for increasing the speed of the calculation process. Furthermore, by sending output data directly to a displaying device in the high-definition multimedia interface, the communication between the host personal computer (PC) and special-purpose computer was controlled in one direction, which significantly reduced communication time. The system was similar to 7.7 times faster than a PC alone and succeeded in the holographic reproduction of a textured 3D image in real time at 30 frames per second for a 1024 x 1024-pixel hologram. (c) The Authors. Published by SPIE under a Creative Commons Attribution 4.0 International License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

关键词： holography computer-generated hologram field-programmable gate array light-ray information discrete Fourier transform

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Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

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JOURNAL OF ELECTRONIC IMAGING 2023年第1期32卷 013012-013012页

作者： Singh, Pulkit Agrawal, Bhaskar Chaurasiya, Rahul Kumar Acharya, Bibhudendra Natl Inst Technol Raipur Dept Elect & Commun Engn Raipur Chhattisgarh India Maulana Azad Natl Inst Technol Bhopal Dept Elect & Commun Engn Bhopal Madhya Pradesh India

Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission for resource-constrained devices is becoming more insecure. In this paper, two hardware implementations for KLEIN block cipher are proposed that can provide security to encrypt different sets of images under resource-constrained applications (such as wireless sensor network, radio frequency identification, IoT etc.). An improvement in maximum operating frequency of 32.72% and 75.66% in the proposed serial and pipelined architectures is observed compared with the state-of-the-art design, respectively. The implemented pipelined architecture yields high throughput of 1840.15 MHz, and the serialized architecture implies 108 numbers of slices implemented on field-programmable gate array (FPGA) xc5vlx50t-3ff1136 device. On application-specific integrated circuit (ASIC) platform, the proposed serialized KLEIN implementation consumed less area in terms of gate equivalent. The existing solution was also subjected to changing correlation coefficients, number of pixels changing rate, unified average changing intensity, and entropy values. The simulation results validate the effectiveness of the performance of the proposed encryption scheme.

关键词： security lightweight cryptography field-programmable gate array application-specific integrated circuit image encryption

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FPGA-Based Implementation of Finite Set-MPC for a VSI System Using XSG-Based Modeling

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ENERGIES 2020年第1期13卷 260页

作者： Singh, Vijay Kumar Tripathi, Ravi Nath Hanamoto, Tsuyoshi Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Fukuoka 8080196 Japan Kyushu Inst Technol Next Generat Power Elect Res Ctr Fukuoka 8080196 Japan

Finite set-model predictive control (FS-MPC) is used for power converters and drives having unique advantages as compared to the conventional control strategies. However, the computational burden of the FS-MPC is a primary concern for real-time implementation. field programmable gate array (FPGA) is an alternative and exciting solution for real-time implementation because of the parallel processing capability, as well as, discrete nature of the hardware platform. Nevertheless, FPGA is capable of handling the computational requirements for the FS-MPC implementation, however, the system development involves multiple steps that lead to the time-consuming debugging process. Moreover, specific hardware coding skill makes it more complex corresponding to an increase in system complexity that leads to a tedious task for system development. This paper presents an FPGA-based experimental implementation of FS-MPC using the system modeling approach. Furthermore, a comparative analysis of FS-MPC in stationary alpha beta and rotating dq frame is considered for simulation as well as experimental result. The FS-MPC for a three-phase voltage source inverter (VSI) system is developed in a realistic digital simulator integrated with MATLAB-Simulink. The simulated controller model is further used for experimental system implementation and validation using Xilinx FPGA: Zedboard Zynq Evaluation and Development Kit. The digital simulator termed as Xilinx system generator (XSG) provided by Xilinx is used for modeling-based FPGA design.

关键词： field-programmable gate array finite set-model predictive control model-based design voltage source inverter Xilinx system generator

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Real-time post-processing for physical-layer secure key distribution in fiber networks

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OPTICS COMMUNICATIONS 2023年 529卷

作者： Cao, Ying Zhang, Liuming Huang, Xinran Hu, Weisheng Yang, Xuelin Shanghai Jiao Tong Univ Key Lab Adv Opt Commun Syst & Nerworks Shanghai 200240 Peoples R China

Physical-layer secure key distribution (PLSKD) in fiber networks provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time high-speed post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including double -threshold quantization, information reconciliation (IR) with Bose-Chaudhuri-Hocquenghem code, and privacy amplification (PA) with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. The throughput of post-processing is optimized by pipeline design approach with the parallel processing capability of FPGA, where the maximum data throughputs are 50, 57.1, and 332.5 Mb/s for the quantization, IR, and PA, respectively. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks.

关键词： Secure key distribution Post-processing Quantization Information reconciliation Privacy amplification field-programmable gate array

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FPGA-Based Hierarchical Configuration Method for Conservation-Oriented Ecological Garden Landscape for a Smart City Development

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JOURNAL OF TESTING AND EVALUATION 2023年第3期51卷 1555-1570页

作者： Yu, Jia Yang, Rui Shenyang Univ Coll Life Sci & Bioengn Shenyang 110044 Peoples R China Shenyang Vanke Real Estate Dev Co Ltd Design Dept Shenyang 110044 Peoples R China

More and more attention is paid to development and conservation at home. In response to national policies, this paper proposes a field-programmable gate array (FPGA)-based hierar-chical configuration method for conservation-oriented ecological garden landscape to build sustainable ecological garden landscapes. Following the principles of uniformity, adapting measures to local conditions, and aesthetics in hierarchical configuration of conservation -oriented ecological garden landscape, this paper gives comprehensive consideration to exami-nation factors and landscape plant rationality in hierarchical configuration and takes scenic beauty estimates to evaluate the plant landscape configuration effect. Under the guidance of hierarchical configuration principles and evaluation indicators for conservation-oriented ecological garden landscape, this paper adopts the FPGA partition algorithm to design the hierarchical conservation design model of the garden landscape. In the subsequent hierarchical configuration of ecological garden landscape, the lowest energy consumption is maintained, plant communities are reasonably collocated to achieve hierarchical configuration of the gar-den landscape, and energy consumption in the landscape is reduced through measures such as material and water conservation, thus achieving hierarchical configuration of conservation -oriented ecological garden landscape. Experimental research results of a forest park in Quanzhou conclude that this method can achieve hierarchical configuration of the ecological garden landscape in the forest park. Plant collocation is reasonable in the more aesthetic and concise landscape configuration. At the same time, the configuration process saves water re-sources and reduces energy consumption, demonstrating the advantage of low configuration costs.

关键词： field-programmable gate array conservation-oriented ecology garden landscape hierarchical configuration

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CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution

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IEEE ACCESS 2020年 8卷 187754-187765页

作者： Lee, Sumin Joo, Sunghwan Ahn, Hong Keun Jung, Seong-Ook Yonsei Univ Sch Elect & Elect Engn Seoul 03722 South Korea

The convolutional neural network (CNN)-based super-resolution (SR) has shown outstanding performance in the field of computer vision. The implementation of inference hardware for CNN-based SR has suffered from the intensive computation with severely unbalanced computation load among layers. Various light-weighted SR networks have been researched with little performance degradation. However, the hardware-efficient dataflow is also required to efficiently accelerate inference hardware within limited resources. In this article, we propose the hardware-efficient dataflow of CNN-based SR that reduces computation load by increasing data reuse and increases process element (PE) utilization by balancing the computation load among layers for high throughput. In the proposed dataflow, row-wise pixels in the receptive field are computed by circularly shifting memory addresses to maximize data reuse. The partial convolution is exploited in a layer-based pipeline architecture to relieve intensive computation in a single pipeline stage. The delay-balancing with adjusting parallelism is employed for balancing computations precisely in the overall layers. Furthermore, the inference hardware of CNN-based SR is implemented for 4K ultrahigh definition at 60 fps on a field-programmable gate array (FPGA). For hardware-friendly computation, the quantization of activation and weight is adopted. The proposed hardware shows an average peak signal-to-noise ratio of 36.42 dB in the Set-5 dataset with a memory usage of 53 KB and an average PE utilization of 76.7% in the overall layers. Thus, it achieves the lowest memory usage and highest PE utilization compared with other inference hardware for CNN-based SR.

关键词： Convolutional neural network dataflow field-programmable gate array inference hardware 4K ultrahigh definition process element utilization super-resolution

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Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V*

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MICROELECTRONICS RELIABILITY 2021年 120卷 114120-114120页

作者： Marques, Ivo Rodrigues, Cristiano Tavares, Adriano Pinto, Sandro Gomes, Tiago Univ Minho Ctr ALGORITMI Braga Portugal

This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores fieldprogrammable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments.

关键词： Dual-core lockstep Design diversity Fault tolerance field-programmable gate array RISC-V Arm

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FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines

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IEEE ACCESS 2020年 8卷 204360-204377页

作者： Kawashima, Ichiro Morie, Takashi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka 8080196 Japan

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

关键词： Chaotic Boltzmann machines combinatorial optimization problems Ising model field-programmable gate array

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