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Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

MICROPROCESSORS AND MICROSYSTEMS 2021年 80卷 103514-103514页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area (smaller gate count on target FPGA) and speed for the same target board.

关键词： Hardware description language Register transfer language field-programmable gate array High-Level Synthesis Harris corner detection Vivado MATLAB HDL coder

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Akcelerace lineárního genetického programování v hardware

Akcelerace lineárního genetického programování v hardwa...

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作者： Ťupa, Josef Brno University of Technology

Tato práce se zabývá návrhem a implementací hardwarové akcelerace lineárního genetického programování symbolické regrese. Práce obsahuje teoretický... 详细信息

Tato práce se zabývá návrhem a implementací hardwarové akcelerace lineárního genetického programování symbolické regrese. Práce obsahuje teoretický úvod do problematiky moderních metod návrhu hardware a genetického programování. V dalších částech práce je popsán návrh a implementace akcelerátoru LGP pro symbolickou regresi.

关键词： Hardwarová akcelerace programovatelná hradlová pole FPGA VHDL lineární genetické programování symbolická regrese. Hardware acceleration field-programmable gate array FPGA VHDL linear genetic programming symbolic regression. Text

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Implementace protokolu CAN pro FITkit

Implementace protokolu CAN pro FITkit

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作者： Jančo, Tomáš Brno University of Technology

Tato bakalářská práce rozebíra principy komunikace na sběrnici CAN a návrh a implementaci řadiče této sběrnice. Řadič je implementovaný v jazyze VHDL pro školní vývojovou... 详细信息

Tato bakalářská práce rozebíra principy komunikace na sběrnici CAN a návrh a implementaci řadiče této sběrnice. Řadič je implementovaný v jazyze VHDL pro školní vývojovou platformu FITKit. Dále práce popisuje návrh obvodů fyzické vrstvy pro připojení FITKit-u na sběrnici.

关键词： CAN sběrnice řadič programovatelné hradlové pole VHDL FITkit CAN bus controller field-programmable gate array VHDL FITkit Text

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Featured town planning based on FPGA and sensors

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MICROPROCESSORS AND MICROSYSTEMS 2021年 81卷 103670-103670页

作者： Song, Xizhong Guo, Yanmo Huanghuai Univ Sch Informat Engn Zhumadian 463000 Henan Peoples R China Huzhou Univ Huzhou 313000 Zhejiang Peoples R China

Sensors are integrated to manage the City?s property information technology. Collect data because these services are the foundation, and the sensor network is an integral part of town planning. Wireless sensors are installed in various locations and thus have the potential for remote data transfer to reduce layer consumption and maintenance costs;Small built-in sensors are much needed. The reason for each sensor?s vital needs, and town planning of the prerequisite information, integrated sensor systems, has developed the concept of town planning. Ann FPGA can be used to solve all the problems that can be calculated. This FPGA is evidenced by the fact that it can implement the microprocessor as a Micro frame or Altera Nios II soft Xilinx. The most important thing is that reverse planning in town design clarifies the importance of landscape design by around town planning. To find the concept of the outline town planning from the perspective of town design, highlight the critical touchpoint in the smart town landscape system, and lead smart, strong principles and town design, planning, and creation. This role is, for sustainable development, the City is effectively Town Development, and it is possible to perform a beautiful town landscape.

关键词： Town planning field-programmable gate array Town landscape design

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Hardware Fuzzy Scheduler for Real-Time Independent Tasks

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2022年第9期31卷 2250155-2250155页

作者： Slimani, Khaled Hadaoui, Rebiha Lalam, Mustapha Univ Mouloud Mammeri Tizi Ouzou Fac Genie Elect & Informat Lab Rech Informat LARI BP 17 RP Tizi Ouzou 15000 Algeria

Several scheduling algorithms that have been proposed for Real-Time Operating System (RTOS) are supposed to be optimal. However, optimal scheduling is only theoretical due to the possibility of system overload where it cannot meet the deadlines of tasks. Besides, these algorithms are implemented in the RTOS, which generates additional overheads that can lead to the "nonscheduling" of certain independent tasks. In this paper, we propose an original solution for nonschedulable independent tasks in embedded systems. This solution, named Hybrid Fuzzy Earliest Deadline First Scheduling algorithm (HFEDFS), is based on the Earliest Deadline First algorithm (EDF) and Fuzzy Logic. It is characterized by a rejection policy and a rescheduling mechanism. The experimental results show that our proposed algorithm improves the system's performance. To reduce extra overheads of RTOS, this algorithm is implemented on a field-programmable gate array (FPGA) circuit (Xilinx Virtex-5 LX50T-1156 board from DIGILENT).

关键词： Embedded systems Real-Time Operating System scheduling deadline Fuzzy Logic field-programmable gate array

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FPGA-Based Controller for a Permanent-Magnet Synchronous Motor Drive Based on a Four-Level Active-Clamped DC-AC Converter

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ENERGIES 2018年第10期11卷 2639-2639页

作者： Nicolas-Apruzzese, Joan Lupon, Emili Busquets-Monge, Sergio Conesa, Alfonso Bordonau, Josep Garcia-Rojas, Gabriel Univ Politecn Cataluna Elect Engn Dept E-08028 Barcelona Spain

This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications.

关键词： DC-link voltage balancing field-oriented control field-programmable gate array multilevel active-clamped converter motor drive

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Hardware architecture for full analytical Fraunhofer computer-generated holograms

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OPTICAL ENGINEERING 2015年第9期54卷 095101-095101页

作者： Pang, Zhi-Yong Xu, Zong-Xi Xiong, Yi Chen, Biao Dai, Hui-Min Jiang, Shao-Ji Dong, Jian-Wen Sun Yat Sen Univ State Key Lab Optoelect Mat & Technol Guangzhou 510275 Guangdong Peoples R China Sun Yat Sen Univ Sch Phys & Engn Guangzhou 510275 Guangdong Peoples R China

Hardware architecture of parallel computation is proposed for generating Fraunhofer computer-generated holograms (CGHs). A pipeline-based integrated circuit architecture is realized by employing the modified Fraunhofer analytical formulism, which is large scale and enables all components to be concurrently operated. The architecture of the CGH contains five modules to calculate initial parameters of amplitude, amplitude compensation, phases, and phase compensation, respectively. The precalculator of amplitude is fully adopted considering the "reusable design" concept. Each complex operation type (such as square arithmetic) is reused only once by means of a multichannel selector. The implemented hardware calculates an 800 x 600 pixels hologram in parallel using 39,319 logic elements, 21,074 registers, and 12,651 memory bits in an Altera field-programmable gate array environment with stable operation at 50 MHz. Experimental results demonstrate that the quality of the images reconstructed from the hardware-generated hologram can be comparable to that of a software implementation. Moreover, the calculation speed is approximately 100 times faster than that of a personal computer with an Intel i5-3230M 2.6 GHz CPU for a triangular object. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： computer-generated hologram field-programmable gate array Fraunhofer real time

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Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2019年第14期28卷

作者： Hariharan, I Kannan, M. Anna Univ Dept Elect Engn MIT Campus Chennai 600044 Tamil Nadu India

Modern embedded systems are packed with dedicated field programmable gate arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

关键词： Configuration mapping field-programmable gate array multimedia application optimal-replacement policy reconfiguration overheads scheduling

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Human Activity Recognition Based on Point Clouds from Millimeter-Wave Radar

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APPLIED SCIENCES-BASEL 2024年第22期14卷 10764页

作者： Lim, Seungchan Park, Chaewoon Lee, Seongjoo Jung, Yunho Korea Aerosp Univ Sch Elect & Informat Engn Goyang 10540 South Korea Sejong Univ Dept Elect Engn Seoul 05006 South Korea Sejong Univ Dept Convergence Engn Intelligent Drone Seoul 05006 South Korea Korea Aerosp Univ Dept Smart Air Mobil Goyang 10540 South Korea

Human activity recognition (HAR) technology is related to human safety and convenience, making it crucial for it to infer human activity accurately. Furthermore, it must consume low power at all times when detecting human activity and be inexpensive to operate. For this purpose, a low-power and lightweight design of the HAR system is essential. In this paper, we propose a low-power and lightweight HAR system using point-cloud data collected by radar. The proposed HAR system uses a pillar feature encoder that converts 3D point-cloud data into a 2D image and a classification network based on depth-wise separable convolution for lightweighting. The proposed classification network achieved an accuracy of 95.54%, with 25.77 M multiply-accumulate operations and 22.28 K network parameters implemented in a 32 bit floating-point format. This network achieved 94.79% accuracy with 4 bit quantization, which reduced memory usage to 12.5% compared to existing 32 bit format networks. In addition, we implemented a lightweight HAR system optimized for low-power design on a heterogeneous computing platform, a Zynq UltraScale+ ZCU104 device, through hardware-software implementation. It took 2.43 ms of execution time to perform one frame of HAR on the device and the system consumed 3.479 W of power when running.

关键词： millimeter-wave radar 3D point cloud human activity recognition field-programmable gate array

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FPGA implementation of QUasi-Affine TRansformation evolutionary algorithm

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KNOWLEDGE-BASED SYSTEMS 2023年第1期276卷

作者： Pan, Jeng-Shyang Yang, Qingyong Chou, Jyh-Horng Hu, Chia-Cheng Chu, Shu-Chuan Shandong Univ Sci & Technol Coll Comp Sci & Engn Qingdao 266590 Peoples R China Chaoyang Univ Technol Dept Informat Management Taichung Taiwan Kaohsiung Med Univ Dept Healthcare Adm & Med Informat Kaohsiung 807 Taiwan Feng Chia Univ Dept Mech & Comp Aided Engn Taichung 407 Taiwan Yango Univ Coll Artificial Intelligence Fuzhou 330015 Peoples R China

The QUasi-Affine TRansformation Evolutionary (QUATRE) algorithm, a new intelligence optimization algorithm, has been widely used in many optimization fields. In this paper, a hardware-based QUATRE algorithm is designed and implemented on a field-programmable gate array (FPGA). To facilitate the implementation of the QUATRE algorithm on hardware, this paper simplifies the co-evolutionary matrix generation process. Compared with the original QUATRE algorithm, the simplified QUATRE algorithm may reduce latency and resource occupation. The Vivado High-Level Synthesis (HLS) design tool is used to complete the IP core design of the QUATRE algorithm. Through the benchmark function test under different population sizes, compared with the QUATRE algorithm implemented by software, both the running speed and optimization performance of the QUATRE algorithm implemented by hardware are significantly better than the former. Compared with the GA, DE, and PSO algorithms implemented by hardware, the QUATRE algorithm also shows strong competitiveness.& COPY;2023 Elsevier B.V. All rights reserved.

关键词： QUasi-Affine TRansformation evolutionary algorithm field-programmable gate array Vivado high-level synthesis Hardware implementation

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