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FPGA Implementation for 24.576-Gbit/s Optical PAM4 Signal Transmission with MLP-Based Digital Pre-Distortion

SENSORS 2024年第23期24卷 7872页

作者： Hu, Sheng Zheng, Tianqi Bian, Chengzhen Yang, Xiongwei Sun, Xinda Zhu, Zonghui Gou, Yumeng Meng, Yuanxiao Zhang, Jie Ge, Jingtao Li, Yichen Wang, Kaihui Fudan Univ State Key Lab Integrated Chips & Syst Shanghai 200433 Peoples R China

In this work, we implemented a short-reach real-time optical communication system using MLP for pre-distortion. Lookup table (LUT) algorithms are commonly employed for pre-distortion in intensity modulation and direct detection (IM/DD) systems. However, storage limitations typically restrict the LUT pattern length to 9, limiting its effectiveness in compensating for nonlinear effects. A multilayer perceptron (MLP) can overcome this limitation by predicting errors and generating pre-distorted signals, thus replacing the extensive storage requirements of LUTs with minimal computational resources. The MLP-based digital pre-distortion (MLP-DPD) technique enables the creation of long-pattern LUTs for improved nonlinear compensation. In this work, an MLP-DPD scheme was implemented on a field-programmable gate array (FPGA). The FPGA was used to generate a 14.7456 GBaud pre-distorted pulse amplitude modulation 4-level (PAM4) signal. This signal was then transmitted over 20 km of standard single-mode fiber (SSMF). At the receiver, the parallel constant modulus algorithm (PCMA) was applied for signal processing. The bit error rate (BER) achieved met the 2.4 x 10-2 threshold for soft-decision forward error correction (SD-FEC), enabling a net transmission bit rate of 24.576 Gbit/s. This approach demonstrates the feasibility of using MLP-DPD for effective nonlinear compensation in high-speed optical communication systems with limited resources.

关键词： digital pre-distortion real-time communication field-programmable gate array pulse amplitude modulation 4-level intensity modulation direct detection

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FPGA-Based Implementation of MMC Control Based on Sorting Networks

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ENERGIES 2018年第9期11卷 2394-2394页

作者： Ricco, Mattia Mathe, Laszlo Monmasson, Eric Teodorescu, Remus Aalborg Univ Dept Energy Technol DK-9100 Aalborg Denmark Cergy Pontoise Univ SATIE Lab F-95031 Cergy Pontoise France

In Modular Multilevel Converter (MMC) applications, the balancing of the capacitor voltages is one of the most important issues for achieving the proper behavior of the MMC. The Capacitor Voltage Balancing (CVB) control is usually based on classical sorting algorithms which consist of repetitive/recursive loops. This leads to an increase of the execution time when many Sub-Modules (SMs) are employed. When the execution time of the balancing is longer than the sampling period, the proper operation of the MMC cannot be ensured. Moreover, due to their inherent sequential operation, sorting algorithms are suitable for software implementation (microcontrollers or DSPs), but they are not appropriate for a hardware implementation. Instead, in this paper, Sorting Networks (SNs) are proposed due to their convenience for implementation in FPGA devices. The advantages and the main challenges of the Bitonic SN in MMC applications are discussed and different FPGA implementations are presented. Simulation results are provided in normal and faulty conditions. Moreover, a comparison with the widely used bubble sorting algorithm and max/min approach is made in terms of execution time and performance. Finally, hardware-in-the-loop results are shown to prove the effectiveness of the implemented SN.

关键词： modular multilevel converters capacitor voltage balancing sorting networks field-programmable gate array

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Time-Sliced Architecture for Efficient Accelerator to Detrend High-Definition Electroencephalograms

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2022年 71卷 1页

作者： Mittal, Rakshit Prince, A. Amalin Fredo, Agastinose Ronickom Jac Inst Polytech Paris Dept INFRES LTCI Lab Telecom Paris F-91120 Palaiseau France Birla Inst Technol & Sci Dept Elect & Elect Engn Sancoale 403726 Goa India Indian Inst Technol BHU Sch Biomed Engn Varanasi 221005 Uttar Pradesh India

Measuring electroencephalography (EEG) signals has a variety of important applications. Most processing systems use statistical machine learning algorithms. To increase accuracy of such systems, more data are measured in the form of increased channel count, called high-definition EEG (HD-EEG). EEG processing is hampered by noise from different instruments. While traditional detrending algorithms are highly resource-intensive, the problem is compounded for HD-EEG detrending. The generic-compounding architecture is not scalable. In such an architecture, one instance of the hardware accelerator is used for each channel. This is unsuitable for wearable devices which have limited computational and energy resources. In this article, we propose a time-sliced architecture to optimize resource and power utilization for a multi-channeled system. This is accomplished using time-division multiplexers and demultiplexers to share resources between different channels. The adaptive maximum-mean-minimum (AMaMeMi) filter is a computationally efficient algorithm, reported earlier for detrending EEGs. We apply guidelines of the proposed architecture, on the AMaMeMi filter, to design an efficient HD-EEG detrending hardware accelerator. The proposed accelerator is implemented for various channel counts. We use the Xilinx field-programmable gate array with part number XC7VX980T-1FFG1930 for implementation. We verify the correctness of the proposed architecture by comparing its output with that of the generic-compounding architecture. For a 1024-channeled system, the proposed time-sliced architecture provides 99% reduction in lookup table utilization, 70% in flip-flop utilization, 95% in area utilization, and 70% in estimated power utilization.

关键词： Electroencephalography Computer architecture Hardware acceleration Registers Time division multiplexing Random access memory Signal processing algorithms Detrending electroencephalograms (EEGs) field-programmable gate array power efficiency resource efficiency

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Independent innovation capability of high-tech enterprises based on FPGA processor and dynamic reconfigurable technology

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MICROPROCESSORS AND MICROSYSTEMS 2021年 81卷 103799-103799页

作者： Li, Weiqing Zhang, Dan Zhejiang Int Studies Univ Sch Int Econ & Tourism Management Hangzhou 310023 Zhejiang Peoples R China Zhejiang A&F Univ Taozhu Business Sch Jiyang Coll Zhuji 311800 Zhejiang Peoples R China

Independent Innovation Capability of High-Tech Enterprises Based on the attributes of cutting edge endeavours, the foundation of a suitable assessment record framework for the limit of cutting edge ventures? autonomous advancement capacities, utilizing the information originates from, and afterward the far reaching positioning of free development abilities of various undertakings area is accomplished through composite score figuring. Machine Learning algorithmic climate and related movement image arrangement. In method our strategy depends on the utilization of Inception to remove different movement classes of highlights and neural organizations. Volleyball, badminton, and have been utilized for investigation and grouping. So as to check the adequacy of the system and, correlation has been finished with different groupings like Random Forest, and Machine Learning The outcomes show that the degree of free advancement capacity of ventures in our area isn?t high, separated. At long last, as indicated by the consequences of the investigation, we set forward some Camille measures and give a few proposals to expand autonomous advancement capacity. field-programmable gate array (FPGA)-based equipment and programming drives keen calculations to handle these utilizing temperature and dampness sensor test information. This strategy actualizes a mechanical Internet of Things framework and shows of the measure of FPGA in equipment assets, diminishing a huge exhibition and asset use.

关键词： Independent Innovation High-Tech Enterprises High Separated field-programmable gate array Machine Learning algorithmic

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EMPLOYING FPGA DSP BLOCKS FOR TIME-TO-DIGITAL CONVERSION

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METROLOGY AND MEASUREMENT SYSTEMS 2019年第4期26卷 631-643页

作者： Kwiatkowski, Pawel Mil Univ Technol Fac Elect Gen S Kaliskiego 2 PL-00918 Warsaw Poland

The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.

关键词： time-to-digital converter time coding line time interval counter digital signal processing field-programmable gate array

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An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

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IEEE-ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS 2015年第5期12卷 1034-1047页

作者： Xin, Yao Li, Will X. Y. Zhang, Zhaorui Cheung, Ray C. C. Song, Dong Berger, Theodore W. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing 210094 Jiangsu Peoples R China Univ So Calif Ctr Neural Engn Dept Biomed Engn Los Angeles CA 90089 USA

Neural coding is an essential process for neuroprosthetic design, in which adaptive filters have been widely utilized. In a practical application, it is needed to switch between different filters, which could be based on continuous observations or point process, when the neuron models, conditions, or system requirements have changed. As candidates of coding chip for neural prostheses, low-power general purpose processors are not computationally efficient especially for large scale neural population coding. Application specific integrated circuits (ASICs) do not have flexibility to switch between different adaptive filters while the cost for design and fabrication is formidable. In this research work, we explore an application specific instruction set processor (ASIP) for adaptive filters in neural decoding activity. The proposed architecture focuses on efficient computation for the most time-consuming matrix/vector operations among commonly used adaptive filters, being able to provide both flexibility and throughput. Evaluation and implementation results are provided to demonstrate that the proposed ASIP design is area-efficient while being competitive to commercial CPUs in computational performance.

关键词： Neuroprosthetics neural coding adaptive filter application specific instruction set processor field-programmable gate array

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Rethinking arithmetic for deep neural networks

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PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2020年第2166期378卷 20190051-20190051页

作者： Constantinides, G. A. Imperial Coll London EEE Dept London England

We consider efficiency in the implementation of deep neural networks. Hardware accelerators are gaining interest as machine learning becomes one of the drivers of high-performance computing. In these accelerators, the directed graph describing a neural network can be implemented as a directed graph describing a Boolean circuit. We make this observation precise, leading naturally to an understanding of practical neural networks as discrete functions, and show that the so-called binarized neural networks are functionally complete. In general, our results suggest that it is valuable to consider Boolean circuits as neural networks, leading to the question of which circuit topologies are promising. We argue that continuity is central to generalization in learning, explore the interaction between data coding, network topology, and node functionality for continuity and pose some open questions for future research. As a first step to bridging the gap between continuous and Boolean views of neural network accelerators, we present some recent results from our work on LUTNet, a novel field-programmable gate array inference approach. Finally, we conclude with additional possible fruitful avenues for research bridging the continuous and discrete views of neural networks. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'.

关键词： neural network computing accelerator field-programmable gate array

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Ultra-low-light-level digital still camera for autonomous underwater vehicle

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OPTICAL ENGINEERING 2019年第1期58卷 013106-013106页

作者： Wu, Houde Hou, Yuchen Xu, Wenhai Zhao, Ming Dalian Maritime Univ Informat Sci & Technol Coll Dalian Peoples R China

In deep ocean applications, a camera's viewing range is related to its low-light-level performance. Hence, a high-resolution ultra-low-light-level digital still camera (thereafter L3DSC), designed from the ground up for deep ocean autonomous underwater vehicle (AUV) imaging, is presented. A high-resolution (1024 x 1024) electron-multiplying CCD (EMCCD) is adopted as an image sensor to ensure low-light capability. A thermo electric cooler (TEC) is employed to lower image sensor temperature to promote low-light-level performance. Totem pole circuits that are able to generate 50-V pulse wave at 10 MHz are implemented to drive the EM pin, and power consumption of the circuit is optimized. An EMCCD digital image is buffered in a field-programmable gate array (FPGA) and then transferred through USB interface to a solid-state drive (SSD), which is installed in the image storage unit. The camera is controlled by AUV via Ethernet, and image data stored in the camera could be downloaded via the same interface after AUV retrieved from the sea. The camera module is mounted into a 6000-m depth-rate titanium alloy housing. The diagonal field of view is measured to be 58.4 deg in air. Experiments show that the minimum scene illumination of L3DSC is better than 5 x 10(-4) Lux;underwater imaging distance is longer than 10 m, and total image data capacity is 200 gigabytes. These results demonstrate the camera's low-light-level imaging performance and feasibility for AUV applications. (C) 2019 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： low-light-level camera electron-multiplying CCD autonomous underwater vehicle field-programmable gate array

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FPGA Implementation of Keyword Spotting System Using Depthwise Separable Binarized and Ternarized Neural Networks

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SENSORS 2023年第12期23卷 5701-5701页

作者： Bae, Seongwoo Kim, Haechan Lee, Seongjoo Jung, Yunho Korea Aerosp Univ Sch Elect & Informat Engn Goyang Si 10540 South Korea Sejong Univ Dept Semicond Syst Engn Seoul 05006 South Korea Sejong Univ Inst Semicond & Syst IC Seoul 05006 South Korea Sejong Univ Dept Convergence Engn Intelligent Drone Seoul 05006 South Korea Korea Aerosp Univ Dept Smart Air Mobil Goyang Si 10540 South Korea

Keyword spotting (KWS) systems are used for human-machine communications in various applications. In many cases, KWS involves a combination of wake-up-word (WUW) recognition for device activation and voice command classification tasks. These tasks present a challenge for embedded systems due to the complexity of deep learning algorithms and the need for optimized networks for each application. In this paper, we propose a depthwise separable binarized/ternarized neural network (DS-BTNN) hardware accelerator capable of performing both WUW recognition and command classification on a single device. The design achieves significant area efficiency by redundantly utilizing bitwise operators in the computation of the binarized neural network (BNN) and ternary neural network (TNN). In a complementary metal-oxide semiconductor (CMOS) 40 nm process environment, the DS-BTNN accelerator demonstrated significant efficiency. Compared with a design approach where BNN and TNN were independently developed and subsequently integrated as two separate modules into the system, our method achieved a 49.3% area reduction while yielding an area of 0.558 mm(2). The designed KWS system, which was implemented on a Xilinx UltraScale+ ZCU104 field-programmable gate array (FPGA) board, receives real-time data from the microphone, preprocesses them into a mel spectrogram, and uses this as input to the classifier. Depending on the order, the network operates as a BNN or a TNN for WUW recognition and command classification, respectively. Operating at 170 MHz, our system achieved 97.1% accuracy in BNN-based WUW recognition and 90.5% in TNN-based command classification.

关键词： binarized neural network field-programmable gate array keyword spotting ternarized neural network

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A Novel FPGA-Based Architecture for Fast Automatic Target Detection in Hyperspectral Images

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REMOTE SENSING 2019年第2期11卷 146-146页

作者： Lei, Jie Wu, Lingyun Li, Yunsong Xie, Weiying Chang, Chein-I Zhang, Jintao Huang, Biying Xidian Univ Sch Telecommun Engn State Key Lab Integrated Serv Networks Xian 710071 Peoples R China Univ Maryland Baltimore Cty Dept Comp Sci & Elect Engn 1000 Hilltop Circle Baltimore MD 21250 USA

Onboard target detection of hyperspectral imagery (HSI), considered as a significant remote sensing application, has gained increasing attention in the latest years. It usually requires processing huge volumes of HSI data in real-time under constraints of low computational complexity and high detection accuracy. Automatic target generation process based on an orthogonal subspace projector (ATGP-OSP) is a well-known automatic target detection algorithm, which is widely used owing to its competitive performance. However, ATGP-OSP has an issue to be deployed onboard in real-time target detection due to its iteratively calculating the inversion of growing matrices and increasing matrix multiplications. To resolve this dilemma, we propose a novel fast implementation of ATGP (Fast-ATGP) while maintaining target detection accuracy of ATGP-OSP. Fast-ATGP takes advantage of simple regular matrix add/multiply operations instead of increasingly complicated matrix inversions to update growing orthogonal projection operator matrices. Furthermore, the updated orthogonal projection operator matrix is replaced by a normalized vector to perform the inner-product operations with each pixel for finding a target per iteration. With these two major optimizations, the computational complexity of ATGP-OSP is substantially reduced. What is more, an FPGA-based implementation of the proposed Fast-ATGP using high-level synthesis (HLS) is developed. Specifically, an efficient architecture containing a bunch of pipelines being executed in parallel is further designed and evaluated on a Xilinx XC7VX690T FPGA. The experimental results demonstrate that our proposed FPGA-based Fast-ATGP is able to automatically detect multiple targets on a commonly used dataset (AVIRIS Cuprite Data) at a high-speed rate of 200 MHz with a significant speedup of nearly 34.3 times that of ATGP-OSP, while retaining nearly the same high detection accuracy.

关键词： hyperspectral image fast automatic target generation process field-programmable gate array high-level synthesis

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