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作者： Leipnitz, Marcos Tomazzoli

The Network Function Virtualization (NFV) paradigm promises to make computer networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, field-programmable gate arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for SRAM-based FPGAs, soft errors on the configuration memory are a significant dependability threat. In this work we present a comprehensive fault tolerance mechanism to deal with configuration faults on the functionality of FPGA-based regular expression matching engines. Moreover, a placement-aware scrubbing mechanism is introduced to reduce the system repair time, improving the system reliability and availability. Experimental results show that the overall failure rate and the system mean time to repair can be reduced in 95% and 90%, respectively, with manageable area and performance costs. ...

关键词： Microeletrônica field-programmable gate array Repair Time Tolerancia : Falhas Fpga Fault-Tolerance Regular Expression Matching Network Function Virtualization Dissertação

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Low-Resource Time-to-Digital Converters for field programmable gate arrays: A Review

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SENSORS 2024年第17期24卷 5512页

作者： Real, Diego Calvo, David Univ Valencia IFIC Inst Fis Corpuscular CSIC C Catedrat Jose Beltran 2 Paterna 46980 Spain

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within field-programmable gate arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process-Voltage-Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field.

关键词： time-to-digital converter field-programmable gate array low-resource time-to-digital converters

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sEMG-Based Hand Gesture Recognition Using Binarized Neural Network

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SENSORS 2023年第3期23卷 1436-1436页

作者： Kang, Soongyu Kim, Haechan Park, Chaewoon Sim, Yunseong Lee, Seongjoo Jung, Yunho Korea Aerosp Univ Sch Elect & Informat Engn Goyang 10540 South Korea Sejong Univ Dept Informat & Commun Engn Seoul 05006 South Korea Sejong Univ Dept Convergence Engn Intelligent Drone Seoul 05006 South Korea Korea Aerosp Univ Dept Smart Air Mobil Goyang 10540 South Korea

Recently, human-machine interfaces (HMI) that make life convenient have been studied in many fields. In particular, a hand gesture recognition (HGR) system, which can be implemented as a wearable system, has the advantage that users can easily and intuitively control the device. Among the various sensors used in the HGR system, the surface electromyography (sEMG) sensor is independent of the acquisition environment, easy to wear, and requires a small amount of data. Focusing on these advantages, previous sEMG-based HGR systems used several sensors or complex deep-learning algorithms to achieve high classification accuracy. However, systems that use multiple sensors are bulky, and embedded platforms with complex deep-learning algorithms are difficult to implement. To overcome these limitations, we propose an HGR system using a binarized neural network (BNN), a lightweight convolutional neural network (CNN), with one dry-type sEMG sensor, which is implemented on a field-programmable gate array (FPGA). The proposed HGR system classifies nine dynamic gestures that can be useful in real life rather than static gestures that can be classified relatively easily. Raw sEMG data collected from a dynamic gesture are converted into a spectrogram with information in the time-frequency domain and transferred to the classifier. As a result, the proposed HGR system achieved 95.4% classification accuracy, with a computation time of 14.1 ms and a power consumption of 91.81 mW.

关键词： surface electromyography hand gesture recognition spectrogram binarized neural network field-programmable gate array

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Conventional and machine learning approaches as countermeasures against hardware trojan attacks

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103295-103295页

作者： Liakos, Konstantinos G. Georgakilas, Georgios K. Moustakidis, Serafeim Sklavos, Nicolas Plessas, Fotis C. Univ Thessaly Sch Engn Dept Elect & Comp Engn CAS Lab Grp Volos Hellas Greece AIDEAS Tallinn Estonia Univ Patras Dept Comp Engn & Informat Patras Hellas Greece

Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits (ICs) in non-trustworthy outsourcing foundries to reduce the cost, thus, leaving space for a synchronous form of virus, known as Hardware Trojan (HT), to be developed. HTs leak encrypted information, degrade device performance or lead to total destruction. To reduce the risks associated with these viruses, various approaches have been developed aiming to prevent and detect them, based on conventional or machine learning methods. Ideally, any undesired modification made to an IC should be detectable by pre-silicon verification/simulation and post-silicon testing. The infected circuit can be inserted in different stages of the manufacturing process, rendering the detection of HTs a complicated procedure. In this paper, we present a comprehensive review of research dedicated to countermeasures against HTs embedded into ICs. The literature is grouped in four main categories;(a) conventional HT detection approaches, (b) machine learning for HT countermeasures, (c) design for security and (d) runtime monitor.

关键词： Hardware security Hardware trojans Integrated circuits Application-specific integrated circuit field-programmable gate array Artificial intelligence Machine learning Detection Prevention Facilitation Design for security Runtime monitor Literature review

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Ergodic sequential logic spiking neural network: reproductions of biologically plausible spatio-temporal phenomena and low-power implementation towards neural prosthesis

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IEICE ELECTRONICS EXPRESS 2024年第8期21卷 20240095-20240095页

作者： Shiomi, Yuta Torikai, Hiroyuki Hosei Univ Grad Sch Sci & Engn Koganei Tokyo 1848485 Japan

A spiking neural network of ergodic sequential logic neuron models is presented. It is shown that the presented network is capable of reproducing various biologically plausible spatio-temporal phenomena (e.g., basic synchronization and complicated chimera phenomenon) observed in the brain. Moreover, it is revealed that the presented network is able to operate with lower power compared to a standard digital -processor -based spiking neural network. It is then discussed that the presented network will be a useful building block in a brain prosthetic device.

关键词： neural prosthesis ergodic sequential logic cellular automaton field-programmable gate array

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Simultaneous injection and measurement chirp division multiplexed Electrical Impedance Tomography and Spectroscopy

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MEASUREMENT 2023年第1期221卷

作者： America, Ezra Luke Tsoeu, Mohohlo Samuel Univ Cape Town P Bag X3 ZA-7701 Cape Town Western Cape South Africa North West Univ P Bag X1290 ZA-2520 Potchefstroom North West South Africa

Electrical Impedance Tomography and Spectroscopy produce cross-sectional images of objects based on the objects' internal impedance distribution. It commonly uses time division multiplexing, frequency division multiplexing, or code division multiplexing. These multiplexing methods have limitations of temporal data inconsistencies when applied to fast-changing objects;spectral inconsistencies due to the application of differ-ent excitation frequencies on different electrodes and inability to achieve frequency difference imaging;and capacitive spikes due to abrupt signal changes, respectively. This paper proposes the novel use of orthogonal chirp division multiplexing to overcome these challenges. Orthogonal chirps are simultaneously injected at all electrodes mounted on the object and potentials measured concurrently. Mathematical formulations and development of a 16-electrode FPGA-based prototype system are presented. It achieves an excitation bandwidth of 1 MHz and 870 frames/second measurements. The system has a position error of 7.74 % and a size error of 3.84 % comparable to other methods.

关键词： Electrical impedance Tomography Spectroscopy EITS field-programmable gate array FPGA Frequency difference FdEIT Mirrored current source Orthogonal chirp division multiplexing Fresnel transform

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A greedy algorithm based Compensation Circuit for Optimizing the Output Statistics of APUF

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MICROELECTRONICS JOURNAL 2023年 131卷

作者： Lian, Jiana Wang, Pengjun Li, Gang Wenzhou Univ Coll Elect & Elect Engn Wenzhou 325035 Peoples R China Wenzhou Univ Coll Comp Sci & Artificial Intelligence Wenzhou 325035 Peoples R China

Physical unclonable function (PUF) can reduce the risk of password leakage of smart connected devices, and has broad application prospects in the field of information security. However, in actual implementation, the designed PUF often deviates greatly due to a lack of experience in using the FPGA platform. Therefore, this paper proposes an APUF adaptive compensation method based on a greedy algorithm. This method can modify the delay by changing the internal transmission path, thereby reducing the skew between APUF paths. First, to enhance the randomness of the APUF output, a compensation circuit with equal delay on the symmetric path of APUF is constructed in a differential manner. Then, the local solution is used to construct the global solution by using the greedy algorithm, which further improves the circuit regulation speed. Finally, the proposed method is imple-mented on FPGA, and the effectiveness of the method is verified by analyzing the statistical characteristics of the output. The experimental results show that the randomness (49.56%), uniqueness (49.08%), and reliability (95.78%) of APUF are close to the ideal values after using the adaptive compensation method. In addition, when implemented on different FPGA platforms and different chip locations, the average randomness of the PUF circuit is 49.46%. Therefore, the method is highly applicable and can be applied to all the same types of FPGA platforms without subsequent adjustments.

关键词： Physical unclonable function Greedy algorithm Differential compensation field-programmable gate array

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Narrowband hybrid PLC/wireless: Transceiver prototype, hardware resource usage and energy consumption

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AD HOC NETWORKS 2019年 94卷 101945-000页

作者： da Costa, Vinicius Lagrota Rodrigues Fernandes, Victor Ribeiro, Moises Vidal Fed Univ Juiz de Fora UFJF LCom Commun Lab Elect Engn Dept Juiz De Fora Brazil Smarti9 LTD Juiz De Fora MG Brazil

This work discusses a prototype of the so-called narrowband (NB) hybrid power line communication (PLC)/Wireless transceiver, which jointly uses parallel power line and wireless channels for providing data communication to the Industry 4.0, Smart Grids and the Internet of Things applications. The prototype introduces a modified version of the IEEE 1901.2 Standard, which was designed to fulfill NB - PLC applications, to implement the media access control (MAC) sublayer and the physical (PHY) layer of a hybrid transceiver that is capable of transmitting data through both power line and wireless channels. Therefore, the NB hybrid PLC/Wireless transceiver prototype is compatible with a NB - PLC transceiver that makes use of the IEEE 1901.2 Standard. Moreover, both transceivers can constitute heterogeneous data communication networks that are capable of improving reliability and coverage. Furthermore, based on a field-programmable gate array (FPGA) device, we discuss the hardware resource usage and energy consumption analyses and the hardware feasibility of implementing a bit correction technique at the link layer of the NB hybrid PLC/Wireless transceiver prototype. We show that the signal/data processing block of the proposed transceiver demands only 1.12 times the energy consumption required by a NB - PLC transceiver based on the IEEE 1901.2 Standard. Moreover, the designed roadmap for this kind of hybrid PLC/wireless transceiver demands 1.5 times the hardware resource usage in comparison to the implementation of the PLC transceiver based on the IEEE 1901.2 Standard. Finally, we show that up 5 bits can be corrected at the link layer level without increasing the clock frequency. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Power line communication Wireless communication field-programmable gate array Internet of Things Smart grid communication Hybrid data communication

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AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

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ENERGIES 2020年第9期13卷 2180-2180页

作者： Huang, Nan-Sheng Chen, Yi-Chung Larsen, Jorgen Christian Manoonpong, Poramate Univ Southern Denmark Maersk Mc Kinney Moller Inst Embodied AI & Neurorobot Lab SDU Biorobot DK-5230 Odense Denmark Tennessee State Univ Dept Elect & Comp Engn Nashville TN 37209 USA

The prediction of a high-level cognitive function based on a proactive brain-machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

关键词： neural network edge device field-programmable gate array hardware acceleration high-level synthesis energy-aware design brain-machine interface

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FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年

作者： Li, Tenglong Li, Jindong Shen, Guobin Zhao, Dongcheng Zhang, Qian Zeng, Yi Univ Chinese Acad Sci Sch Artificial Intelligence Beijing 100049 Peoples R China Chinese Acad Sci Inst Automat Brain Inspired Cognit Intelligence Lab Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Future Technol Beijing 100049 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Chinese Acad Sci Key Lab Brain Cognit & Brain Inspired Intelligence Shanghai 200031 Peoples R China

Spiking Neural Networks (SNNs), with their brain-inspired structure using discrete spikes instead of continuous activations, are gaining attention for their potential of efficient processing on neuromorphic chips. While current SNN hardware accelerators often prioritize temporal spike sparsity, exploiting sparse synaptic weights offers significant untapped potential for even greater efficiency. To address this, we propose FireFly-S, a Sparse extension of the FireFly series. This co-optimized software-hardware design focusing on leveraging dual-side sparsity for acceleration. On the software side, we propose a novel algorithmic optimization framework that combines gradient rewiring for pruning and modified Learned Step Size Quantization (LSQ) tailored for SNNs, which achieves remarkable weight sparsity exceeding 85% and enables efficient 4-bit quantization with negligible accuracy loss. On the hardware side, we present an efficient dual-side sparsity detector employing a Bitmap-based sparse decoding logic to pinpoint the positions of non-zero weights and input spikes. The logic allows for the direct bypassing of redundant computations, thereby enhancing computational efficiency. Different from the overlay architecture adopted by previous FireFly series, we adopt a parametric spatial architecture with inter-layer pipelining that can fully exploit the fine-grained programmability and reconfigurability of field-programmable gate arrays (FPGAs), enabling fast deployment for various models. A spatial-temporal dataflow is also proposed to support such inter-layer pipelining and avoid long-term temporal dependencies. In experiments conducted on the MNIST, DVS-Gesture and CIFAR-10 datasets, the FireFly-S model achieves 85-95% sparsity with 4-bit quantization and the hardware accelerator effectively leverages the dual-side sparsity, delivering outstanding performance metrics of 10,047 FPS/W on MNIST, 3,683 FPS/W on DVS-Gesture, and 2,327 FPS/W on CIFAR-10.

关键词： Spiking neural networks field-programmable gate array hardware accelerator dual-side sparsity software-hardware co-design inter-layer pipelining

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