检索结果-内蒙古大学图书馆

Slant transform applied to electric power quality detection with field programmable gate array design enhanced

INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2010年第5期32卷 428-432页

作者： Hsieh, Cheng-Tao Lin, Jeu-Min Huang, Shyh-Jier Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Kun Shan Univ Dept Elect Engn Tainan Taiwan Far E Univ Dept Elect Engn Tainan Taiwan

In this paper, a slantlet transform is proposed with the field-programmable gate array (FPGA) hardware realization for electrical power system disturbance detection. By embedding the slantlet functions into wavelet basis, the method is anticipated to increase the capability of signal discrimination, hence improving the grasping the disturbance intrusion. Furthermore, with the hardware realization of FPGA chip, the practicality of the method can be better ensured. In order to validate the effectiveness of the proposed approach, several scenarios have been considered and verified with good agreement. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： Electrical power system disturbances Slantlet transform field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

A Soft Computing Approach to Crack Detection and Impact Source Identification with field-programmable gate array Implementation

引用

ADVANCES IN FUZZY SYSTEMS 2013年第unknown期2013卷

作者： Dixit, Arati M. Singh, Harpreet Def Inst Adv Technol DU Dept Comp Engn Pune 411025 Maharashtra India Wayne State Univ Dept Elect & Comp Engn Detroit MI 48202 USA

The real-time nondestructive testing (NDT) for crack detection and impact source identification (CDISI) has attracted the researchers fromdiverse areas. This is apparent fromthe current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposedmethod can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB's fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL). The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA) implementation is done using Xilinx's Spartan 3 FPGA. SynaptiCAD's Verilog Simulators-VeriLogger PRO andModelSim-are used as the software simulation and debug environment.

关键词： Hardware description language Soft computing Nondestructive testing Crack field-programmable gate array Fuzzy logic

来源：评论

学校读者我要写书评

暂无评论

Spiking neural networks on FPGA: A survey of methodologies and recent advancements

引用

NEURAL NETWORKS 2025年 186卷 107256页

作者： Karamimanesh, Mehrzad Abiri, Ebrahim Shahsavari, Mahyar Hassanli, Kourosh van Schaik, Andre Eshraghian, Jason Shiraz Univ Technol Dept Elect Engn Shiraz Iran Radboud Univ Nijmegen Donders Inst Brain Cognit & Behav AI Dept Nijmegen Netherlands Western Sydney Univ MARCS Inst Int Ctr Neuromorph Syst Sydney Australia Univ Calif Santa Cruz Dept Elect Engn Santa Cruz CA USA

The mimicry of the biological brain's structure in information processing enables spiking neural networks (SNNs) to exhibit significantly reduced power consumption compared to conventional systems. Consequently, these networks have garnered heightened attention and spurred extensive research endeavors in recent years, proposing various structures to achieve low power consumption, high speed, and improved recognition ability. However, researchers are still in the early stages of developing more efficient neural networks that more closely resemble the biological brain. This development and research require suitable hardware for execution with appropriate capabilities, and field-programmable gate array (FPGA) serves as a highly qualified candidate compared to existing hardware such as central processing unit (CPU) and graphics processing unit (GPU). FPGA, with parallel processing capabilities similar to the brain, lower latency and power consumption, and higher throughput, is highly eligible hardware for assisting in the development of spiking neural networks. In this review, an attempt has been made to facilitate researchers' path to further develop this field by collecting and examining recent works and the challenges that hinder the implementation of these networks on FPGA.

关键词： Spiking neural network Neuromorphic computing field-programmable gate array Brain-inspired computing Accelerator

来源：评论

学校读者我要写书评

暂无评论

Laser Linewidth Measurement Using an FPGA-Based Delay Self-Homodyne System

引用

PHOTONICS 2025年第3期12卷 203-203页

作者： Bu, Fanqi Zhao, Zhongan Li, Longfei Zhang, Cunwei Li, Tie Qi, Yaoyao Ding, Jie Yan, Bingzheng Zhao, Chen Wang, Yulei Lu, Zhiwei Ding, Yu Bai, Zhenxu Hebei Univ Technol Ctr Adv Laser Technol Tianjin 300401 Peoples R China Hebei Key Lab Adv Laser Technol & Equipment Tianjin 300401 Peoples R China Natl Key Lab Electromagnet Space Secur Tianjin 300401 Peoples R China

Narrow-linewidth lasers play a crucial role in nonlinear optics, atomic physics, optical metrology, and high-speed coherent optical communications. Precise linewidth measurement is essential for assessing laser noise characteristics;however, conventional methods are often bulky, costly, and unsuitable for integrated applications. This paper presents a compact and cost-effective delay self-homodyne system for laser linewidth measurement, leveraging a field-programmable gate array (FPGA)-based data acquisition circuit. By employing fast Fourier transform (FFT) analysis, the system achieves high-precision linewidth measurement in the kHz range. Additionally, by optimizing the fiber length, the system effectively suppresses low-frequency and 1/f noise, providing an integrated and efficient solution for advanced laser characterization with enhanced performance and reduced cost.

关键词： narrow linewidth delay self-homodyne field-programmable gate array fast Fourier transform 1/f noise

来源：评论

学校读者我要写书评

暂无评论

High-speed and reduced energy delay product TCAM on FPGA for network routers

引用

ETRI JOURNAL 2025年第0期

作者： Vadivel, Sridhar Raj Sankara Ramapackiam, Shantha Selvakumari Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi India

Ternary content-addressable memory (TCAM) is widely used in the design of high-speed search engines such as network routers and artificial-intelligence-based applications. However, traditional TCAM designs suffer from two major drawbacks. Static random access memory (RAM)-based TCAMs do one operation at a time, causing the search operation to be suspended while the update operation is in progress, rendering them unsuitable for applications with high-frequency updates. Moreover, during the implementation of wider TCAMs, when the match results are transferred from one slice to another, the last look-up table (LUT) in the slice is always set to logic one, which results in resource wastages. This research aims to overcome the problems associated with traditional TCAM design. The proposed work used six-input (RAM64X1S) LUTs in field-programmable gate arrays by allowing both search and update operations to be performed simultaneously during the data update in a particular LUT. To overcome resource wastage, the proposed design used four RAM64X1S blocks instead of RAM64M blocks. Moreover, the proposed TCAM architecture was considerably simpler, comprising LUTs with AND slicing, thus reducing FPGA resources such as slice registers and slice logic. For TCAM sizes of 512 x 36 and 1024 x 144, the slice utilization was reduced by 17% and 29%, respectively, with their speed being increased by 17% and 26%, respectively. Moreover, the lookup rate and the update rate of the designed TCAMs also improved considerably. The proposed architecture employed high-speed single-cycle searches, making it ideal for fast search applications.

关键词： data compression field-programmable gate array routers static random-access memory ternary content-addressable memory translation lookaside buffers

来源：评论

学校读者我要写书评

暂无评论

Development of a proof-of-principle PET system using multi-time-over-threshold and FPGA without ADC or TDC

引用

NUCLEAR ENGINEERING AND TECHNOLOGY 2025年第5期57卷

作者： Kim, Kyu Bom Kim, Kyuseok Jeong, Hyun-Woo Kim, Yeonkyeong Lee, Su Hwan Yonsei Univ Coll Hlth Sci Dept Radiat Convergence Engn Wonju South Korea Eulji Univ Dept Biomed Engn Songnam South Korea Yonsei Univ Severance Hosp Dept Internal Med Div Pulm & Crit Care MedColl Med Seoul South Korea 2TS Corp 211 Hwarang Ro Seoul 08393 South Korea

The goal of this study was to extend a multi-time-over-threshold (MToT) based multi-channel front-end circuit and field-programmable gate array only data acquisition (DAQ) without analog-to-digital converter or time-todigital converter for the development of a proof-of-principle positron emission tomography (PET) system. The proposed system was configured with two detector modules, each having a 4 x 2 detector block (128 ch/detector module). The performance of the PET system using a 256-channel analog circuit and a DAQ system was evaluated by measuring energy resolution and time resolution. These values were 20 % and 1.5 ns, respectively. The calculated data packet containing energy, time, and position information was formed into 64-bit single event data package and sent to the host computer using USB 3.0 control interface. Experiment results revealed that the spatial resolution was 2.1 mm at the center and 2.2 mm at 20 mm from the center. The Derenzo Phantom based experiment showed sufficient distinguish for Hod-rod of various radius, confirming the viability of the proposed proof-of-principle system.

关键词： Multi-time-over-threshold method field-programmable gate array Analog and digital signal processing Positron emission tomography Proof-of-principle system

来源：评论

学校读者我要写书评

暂无评论

FPGA-based performance evaluation of backstepping control and computed torque control for industrial robots

引用

INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL 2025年第1期19卷 101-132页

作者： Fekik, Arezki Khati, Hocine Azar, Ahmad Taher Hamida, Mohamed Lamine Denoun, Hakim Kamal, Nashwa Ahmad Univ Akli Mohand Oulhadj Bouria Dept Elect Engn Rue Drissi Yahia Bouira 10000 Algeria Nantes Univ Ecole Cent Nantes CNRS LS2NUMR 6004 F-44000 Nantes France Univ Mouloud Mammeri Tizi Ouzou Fac Elect & Comp Engn Dept Automat Design & Drive Prod Syst Lab Tizi Algeria Prince Sultan Univ Coll Comp & Informat Sci Riyadh 11586 Saudi Arabia Prince Sultan Univ Automated Syst & Soft Comp Lab ASSCL Riyadh Saudi Arabia Benha Univ Fac Comp & Artificial Intelligence Banha 13518 Egypt Elect Engn Adv Technol Lab LATAGE Tizi Algeria Cairo Univ Fac Engn Giza 12613 Egypt

In this paper, a comparative study is conducted on two nonlinear control techniques: state feedback control through backstepping and computed torque control. The study focuses on their application to the industrial robot PUMA 560. The primary goal is to assess the trajectory tracking accuracy and speed achieved by these methods. To achieve this objective, both control techniques are employed on the Zed board Zynq FPGA platform, encompassing both simulation and hardware systems. Subsequently, the experimental results are thoroughly analysed and compared, aiming to accentuate the unique advantages and constraints associated with each method.

关键词： field-programmable gate array FPGA backstepping control computed torque control CTC Zed board Zynq PUMA 560

来源：评论

学校读者我要写书评

暂无评论

Using FPGA devices to accelerate the evaluation phase of tree-based genetic programming: an extended analysis

引用

GENETIC PROGRAMMING AND EVOLVABLE MACHINES 2025年第1期26卷 1-48页

作者： Crary, Christopher Piard, Wesley Stitt, Greg Hicks, Benjamin Bean, Caleb Burlacu, Bogdan Banzhaf, Wolfgang Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA Univ Appl Sci Upper Austria Heurist & Evolutionary Algorithms Lab Hagenberg Upper Austria Austria Michigan State Univ Dept Comp Sci & Engn E Lansing MI USA

This paper establishes the potential of accelerating the evaluation phase of tree-based genetic programming through contemporary field-programmable gate array (FPGA) technology. This exploration stems from the fact that FPGAs can sometimes leverage increased levels of both data and function parallelism, as well as superior power/energy efficiency, when compared to general-purpose CPU/GPU systems. In this investigation, we introduce a fixed-depth, tree-based architecture that can fully parallelize tree evaluation for type-consistent primitives that are unrolled and pipelined. We show that our accelerator on a 14nm FPGA achieves an average speedup of 43x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} when compared to a recent open-source GPU solution, TensorGP, implemented on 8nm process-node technology, and an average speedup of 4,902x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} when compared to a popular baseline GP software tool, DEAP, running parallelized across all cores of a 2-socket, 28-core (56-thread), 14nm CPU server. Despite our single-FPGA accelerator being 2.4x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} slower on average when compared to the recent state-of-the-art Operon tool executing on the same 2-processor, 28-core CPU system, we show that this single-FPGA system is 1.4x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym}

关键词： Tree-based genetic programming field-programmable gate array Domain-specific architecture Hardware acceleration

来源：评论

学校读者我要写书评

暂无评论

Educational CT Scanner Model Realization: A Case Study Using Laser Emitter and 3-D Printing

引用

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Prochazka, Michal Kasik, Vladimir Litschmannova, Martina Penhaker, Marek VSB Tech Univ Ostrava Fac Elect Engn & Comp Sci Dept Cybernet & Biomed Engn Ostrava 70800 Czech Republic VSB Tech Univ Ostrava Fac Elect Engn & Comp Sci Dept Appl Math Ostrava 70800 Czech Republic

Understanding the fundamental principles of computed tomography (CT) is essential for future healthcare professionals. To facilitate this learning process, we designed and constructed an educational model that closely resembles a third-generation medical CT scanner. This model enables users to grasp the mechanics of CT scanning, including the movement of the bed's height, bed translation, and gantry rotation. Utilizing a red linear laser, which does not require special safety measures, this model effectively demonstrates the CT scanning process by projecting visible red light beams and collecting projection data with phototransistors. The reconstruction of CT images is achieved using the inverse Radon transform, emphasizing simplicity and educational value over advanced medical CT techniques. Our evaluation of the model revealed that the pixel area was 2.67 mm(2), with bed translation dictating resolution along the bed axis. We observed distortions in the representation of sharp-edged objects during image reconstruction, illustrating potential measurement limits. Based on these findings, two phantoms were created, one of which was reconstructed in 3-D for comparison. This educational CT model provides a valuable tool that bridges the gap between theoretical knowledge and practical application, making the complex field of CT scanning more accessible and comprehensible for students and the public. This model not only enhances the understanding of CT principles but also provides a platform for further exploration and refinement in the field.

关键词： Computed tomography Computational modeling X-ray imaging Image reconstruction Data models Biomedical imaging Biological system modeling X-ray lasers Three-dimensional printing Data acquisition Biomedical engineering education computed tomography (CT) diode lasers field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Optimized FFT Designs for High-Performance LTE and 5G Networks

引用

ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING 2025年 1-20页

作者： Khan, Daud Jan, Latif Zafar, Mohammad Haseeb IQRA Natl Univ Dept Comp Sci Peshawar 25100 Khyber Pakhtunk Pakistan Cardiff Metropolitan Univ Cardiff Sch Technol Cardiff CF5 Wales

This paper proposes a run-time reconfigurable butterfly structure capable of simultaneously performing Radix-8, Radix-4, Radix-3, and Radix-2 Fast Fourier Transform (FFT) computations to cater to the bandwidth requirements of current Long-Term Evolution (LTE), Fifth Generation (5G), and beyond systems. While LTE and 5G promise exceptionally high throughput, ranging from 300 Mbps to 3 Gbps, field-programmable gate array (FPGA) and Application Specific Integrated Circuit vendors face significant challenges in meeting these demands. Efficient implementation strategies are essential for realizing these standards in silicon. Given that FFT is the cornerstone of 5G systems, its computational complexity poses challenges in meeting high throughput requirements. Furthermore, the flexibility to adapt to different bandwidths is crucial in 5G networks. Therefore, a configurable FFT engine that optimizes resource utilization while providing high throughput is highly desirable. This paper presents two FFT architectures based on the proposed reconfigurable butterfly, offering designers the flexibility to choose the most suitable approach for realizing efficient and high-throughput solutions tailored to the requirements of 5G and beyond.

关键词： Fast Fourier transform field-programmable gate array Application specific integrated circuit 5th generation Long-term evolution

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：