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Implementation of a universal replicable DSP core in FPGA devices for cascade audio signal processing applications

Procedia Computer Science 2024年 246卷 2429-2438页

作者： Łukasz Gołka Paweł Poczekajło Robert Suszyński Koszalin University of Technology. ul Śniadeckich 2 75-453 Koszalin Poland

The article presents the concept of a universal DSP core, enabling the creation of systems compliant with various processing architectures, such as Single Instruction, Multiple Data - SIMD, Multiple Instruction, Multiple Data - MIMD. The aim was to facilitate a simpler and faster configuration and programming process for complex and more efficient signal processing systems, while minimizing the need for hardware description languages. The architecture and instruction set for the DSP core are described, allowing for simultaneous addressing of multiple operands in a single instruction. Unidirectional signal flows between cores are proposed, resulting in a reduction of connections and increased performance. The testing process and comparison of results with computations performed in Matlab are described. The paper points out future research directions, such as hardware optimization, increasing the number of cores, developing floating-point computations, and modular system construction. The proposed solutions can significantly impact the efficiency and flexibility of future signal processing systems.

关键词： DSP core replicable core universal core implementation concept signal processing signal processing applications field-programmable gate array FPGA

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A reconfigurable hardware approach to network simulation

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ACM Transactions on Modeling and Computer Simulation 1997年第1期7卷 131–156页

作者： Dimitrios Stiliadis Anujan Varma Univ. of California Santa Cruz

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Autonomous Jerk Oscillator with Cosine Hyperbolic Nonlinearity: Analysis, FPGA Implementation, and Synchronization

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ADVANCES IN MATHEMATICAL PHYSICS 2018年第1期2018卷

作者： Rajagopal, Karthikeyan Kingni, Sifeu Takougang Kuiate, Gaetan Fautso Tamba, Victor Kamdoum Viet-Thanh Pham Def Univ Ctr Nonlinear Dynam Bishoftu Ethiopia Univ Maroua Fac Mines & Petr Ind Dept Mech Petr & Gas Engn POB 46 Maroua Cameroon Univ Bamenda Higher Teacher Training Coll Dept Phys POB 39 Bamenda Cameroon Univ Dschang Fac Sci Dept Phys Lab Elect & Signal Proc LETS POB 67 Dschang Cameroon Hanoi Univ Sci & Technol Sch Elect & Telecommun 01 Dai Co Viet Hanoi Vietnam

A two-parameter autonomous jerk oscillator with a cosine hyperbolic nonlinearity is proposed in this paper. Firstly, the stability of equilibrium points of proposed autonomous jerk oscillator is investigated by analyzing the characteristic equation and the existence of Hopf bifurcation is verified using one of the two parameters as a bifurcation parameter. By tuning its two parameters, various dynamical behaviors are found in the proposed autonomous jerk oscillator including periodic attractor, one-scroll chaotic attractor, and coexistence between chaotic and periodic attractors. The proposed autonomous jerk oscillator has period-doubling route to chaos with the variation of one of its parameters and reverse period-doubling route to chaos with the variation of its other parameter. The proposed autonomous jerk oscillator is modelled on field programmable gate array (FPGA) and the FPGA chip statistics and phase portraits are derived. The chaotic and coexistence of attractors generated in the proposed autonomous jerk oscillator are confirmed by FPGA implementation of the proposed autonomous jerk oscillator. A good qualitative agreement is illustrated between the numerical and FPGA results. Finally synchronization of unidirectional coupled identical proposed autonomous jerk oscillators is achieved using adaptive sliding mode control method.

关键词： Oscillation Hopf bifurcation Coexistence field-programmable gate array Chaos

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Spaceborne synthetic aperture radar imaging mapping methodology based on FPGA-DSP hybrid heterogeneous architecture

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JOURNAL OF ENGINEERING-JOE 2019年第21期2019卷 7313-7317页

作者： Yu, Wenyue Xie, Yizhuang Li, Bingyi Chen, He Liu, Xiaoning Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China DFH Satellite Co Ltd Beijing 100081 Peoples R China

With the development of synthetic aperture radar (SAR) technologies in recent years, the huge amount of remote sensing data bring challenges for high-speed transmission and real-time processing. The general platform with GPU, CPU or digital signal processor (DSP) cannot meet the requirement for short delay and low power. Therefore, a field-programmable gate array-digital signal processor (FPGA-DSP) SAR imaging accelerate platform has become a solution for processing performance with a lower latency and power. In this study, an effective mapping strategy is adopted to the FPGA-DSP hybrid heterogeneous architecture to accelerate the processing performance according to the analysis of Chirp Scaling SAR imaging algorithms. As a proof of concept, a FPGA-DSP hybrid heterogeneous accelerating platform is designed and realised. The platform requires 12 s to focus a stripmap SAR raw data with a granularity of 16,384 x 16,384.

关键词： field programmable gate arrays digital signal processing chips synthetic aperture radar spaceborne radar radar imaging spaceborne synthetic aperture radar FPGA-DSP hybrid heterogeneous architecture synthetic aperture radar technologies remote sensing data high-speed transmission real-time processing FPGA-DSP hybrid heterogeneous accelerating platform stripmap SAR raw data field-programmable gate array mapping strategy digital signal processor chirp scaling SAR imaging radar mapping methodology time 12 0 s

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Development and Application of Ion Current/Cylinder Pressure Cooperative Combustion Diagnosis and Control System

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ENERGIES 2020年第21期13卷 5656页

作者： Zhu, Denghao Deng, Jun Wang, Jinqiu Wang, Shuo Zhang, Hongyu Andert, Jakob Li, Liguang Tongji Univ Sch Automot Studies Shanghai 201804 Peoples R China Tongji Univ Chines Deutsch Hochschulkolleg Shanghai 201804 Peoples R China Rhein Westfal TH Aachen Mechatron Syst Combust Engines D-52074 Aachen Germany

The application of advanced technologies for engine efficiency improvement and emissions reduction also increase the occurrence possibility of abnormal combustions such as incomplete combustion, misfire, knock or pre-ignition. Novel promising combustion modes, which are basically dominated by chemical reaction kinetics show a major difficulty in combustion control. The challenge in precise combustion control is hard to overcome by the traditional engine map-based control method because it cannot monitor the combustion state of each cycle, hence, real-time cycle-resolved in-cylinder combustion diagnosis and control are required. In the past, cylinder pressure and ion current sensors, as the two most commonly used sensors for in-cylinder combustion diagnosis and control, have enjoyed a seemingly competitive relationship, so all related researches only use one of the sensors. However, these two sensors have their own unique features. In this study, the idea is to combine the information obtained from both sensors. At first, two kinds of ion current detection system are comprehensively introduced and compared at the hardware level and signal level. The most promising variant (the DC-Power ion current detection system) is selected for the subsequent experiments. Then, the concept of ion current/cylinder pressure cooperative combustion diagnosis and control system is illustrated and implemented on the engine prototyping control unit. One application case of employing this system for homogenous charge compression ignition abnormal combustion control and its stability improvement is introduced. The results show that a combination of ion current and cylinder pressure signals can provide richer and also necessary information for combustion control. Finally, ion current and cylinder pressure signals are employed as inputs of artificial neural network (ANN) models for combustion prediction. The results show that the combustion prediction performance is better when the inputs ar

关键词： Ion current cylinder pressure cooperative combustion diagnosis and control field-programmable gate array artificial neural network

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Motion-Based Object Location on a Smart Image Sensor Using On-Pixel Memory

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SENSORS 2022年第17期22卷 6538页

作者： Valenzuela, Wladimir Saavedra, Antonio Zarkesh-Ha, Payman Figueroa, Miguel Univ Concepcion Fac Engn Dept Elect Engn Concepcion 4070386 Chile Tech Univ Berlin Elect Engn & Comp Sci Fac Inst Comp Engn & Microelect Embedded Syst Architecture Grp D-10623 Berlin Germany Univ New Mexico Sch Engn Dept Elect & Comp Engn ECE Albuquerque NM 87131 USA

Object location is a crucial computer vision method often used as a previous stage to object classification. Object-location algorithms require high computational and memory resources, which poses a difficult challenge for portable and low-power devices, even when the algorithm is implemented using dedicated digital hardware. Moving part of the computation to the imager may reduce the memory requirements of the digital post-processor and exploit the parallelism available in the algorithm. This paper presents the architecture of a Smart Imaging Sensor (SIS) that performs object location using pixel-level parallelism. The SIS is based on a custom smart pixel, capable of computing frame differences in the analog domain, and a digital coprocessor that performs morphological operations and connected components to determine the bounding boxes of the detected objects. The smart-pixel array implements on-pixel temporal difference computation using analog memories to detect motion between consecutive frames. Our SIS can operate in two modes: (1) as a conventional image sensor and (2) as a smart sensor which delivers a binary image that highlights the pixels in which movement is detected between consecutive frames and the object bounding boxes. In this paper, we present the design of the smart pixel and evaluate its performance using post-parasitic extraction on a 0.35 mu m mixed-signal CMOS process. With a pixel-pitch of 32 mu m x 32 mu mu m, we achieved a fill factor of 28%. To evaluate the scalability of the design, we ported the layout to a 0.18 mu m process, achieving a fill factor of 74%. On an array of 320 x 240 smart pixels, the circuit operates at a maximum frame rate of 3846 frames per second. The digital coprocessor was implemented and validated on a Xilinx Artix-7 XC7A35T field-programmable gate array that runs at 125 MHz, locates objects in a video frame in 0.614 mu s, and has a power consumption of 58 mW.

关键词： smart image sensor smart pixel vision chip intelligent sensor object detection object location motion-based frame difference field-programmable gate array very large scale integration

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Experimental Evaluation of the Performance of a Three-Phase Five-Level Cascaded H-Bridge Inverter by Means FPGA-Based Control Board for Grid Connected Applications

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ENERGIES 2018年第12期11卷 3298-3298页

作者： Viola, Fabio Univ Palermo DEIM Dipartimento Energia Ingn Informaz & Modelli Mate I-90133 Palermo Italy

Over the last decades, plants devoted to the generation of green energy significantly increased their number, together with the demand of same electrical energy, also stored in battery systems. This fact produced the growth of energy conversion systems with advanced performances with respect to the traditional ones. In this circumstance, multilevel converters play a significant role for their great advantages in performances, flexibility, fault-tolerability, employment of renewable energy sources and storage systems and finally yet importantly reduced filter requirements. In this context, this paper faces the performance of a cascaded H-bridge 5 level inverter in terms of harmonic distortion generated and injected into the grid. Through an accurate analysis that takes into account the pulse width modulation (PWM) multicarrier modulation techniques (phase disposition PD, phase opposition disposition POD, alternative phase opposition disposition APOD, phase shifted PS) and related reference signals (sinusoidal reference;third harmonic injection THI reference, switching frequency optimal SFO reference), a framework of distorting harmonics is presented by comparing twelve cases. The results obtained from the simulations are reproduced and validated in a prototype system of five level cascaded H-bridge multilevel inverter. A deep discussion of control and filtering system is provided to justify the choice of the best modulation technique to adopt.

关键词： Cascaded H-bridge multilevel inverter (CHBMI) field-programmable gate array total harmonic distortion (THD) modulation techniques

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Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

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JAPANESE JOURNAL OF APPLIED PHYSICS 2022年第SC期61卷 SC1083-SC1083页

作者： Suzuki, Daisuke Oka, Takahiro Hanyu, Takahiro Univ Aizu Kami Iawase 90 Aizu Wakamatsu Fukushima 9658580 Japan Tohoku Univ Aoba Ku 2-1-1 Katahira Sendai Miyagi 9808577 Japan

A nonvolatile lookup table (NV-LUT) circuit, which is a key component of a field-programmable gate array, is proposed for an energy-efficient yet high-performance binarized convolutional neural network (BCNN) accelerator. Since the active load is distributed to each configuration memory cell, the effect of the parasitic components is greatly reduced. Moreover, the use of a wired-OR logic-circuit style makes it possible to perform a high-speed logic operation. The proposed 6-input NV-LUT circuit using an active-load-localized single-ended circuit style is designed using a 45 nm CMOS technology and the delay is reduced by 30% with only 13% of hardware overhead compared to those of a conventional NV-LUT circuit. It is also demonstrated that the proposed NV-LUT circuit exhibits variation resilience against three process corners. The use of the proposed NV-LUT circuit also makes it possible to reduce 47% of the energy consumption of a BCNN accelerator for digit recognition compared to that of a conventional SRAM-LUT-based implementation.

关键词： field-programmable gate array Lookup Table Nonvolatile Magnetic Tunnel Junction Spin-Orbit Torque Binary Convolutional Neural Network

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Investigation of spatial and temporal characteristics of turbulent-distorted laser radiation during its dynamic phase correction in an adaptive optical system

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QUANTUM ELECTRONICS 2021年第11期51卷 992-999页

作者： Belousov, V. N. Bogachev, V. A. Volkov, M. V. Garanin, S. G. Kudryashov, A., V Nikitin, A. N. Rukosuev, A. L. Starikov, F. A. Sheldakova, Yu, V Shnyagin, R. A. Russian Acad Sci Inst Geosphere Dynam Leninsky Prosp 38Korpus 1 Moscow 119334 Russia Russian Fed Nucl Ctr Inst Laser Phys Res All Russian Sci Res Inst Expt Phys RFNC VNIIEF Prosp Mira 37 Sarov 607188 Nizhny Novgorod Russia Moscow Polytech Univ Ul B Semenovskaya 38 Moscow 107023 Russia

We report the results of the analysis of experiments on dynamic phase correction of laser radiation distorted by a turbulent airflow in an adaptive optical system (AOS) with a Shack - Hartmann wavefront sensor (WFS). A field-programmable gate array is used as the main AOS control element, which provides a closed loop AOS bandwidth of up to 2000 Hz. The WFS is used to estimate the characteristic bandwidth of the generated turbulence nu(turb). Changes in the spatial and temporal spectra of the laser radiation phase, as well as the quality of the beam during its dynamic phase correction at various AOS frequencies, are analysed. It is shown experimentally and by calculation that to ensure a high efficiency of the wavefront correction, the AOS frequency should be at least 20 times higher than nu(turb).

关键词： adaptive optics wavefront sensor field-programmable gate array atmospheric turbulence

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A Deep Learning-Based FPGA Function Block Detection Method With Bitstream to Image Transformation

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IEEE ACCESS 2021年 9卷 99794-99804页

作者： Chen, Minzhen Liu, Peng Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China

In the context of various application scenarios and/or for the sake of strengthening field-programmable gate array (FPGA) security, the system functions of an FPGA design need to be analyzed, which can be achieved by systematically partitioning the FPGA's bitstream into manageable functional blocks and detecting their functionalities thereafter. In this paper, we propose a novel deep learning-based FPGA function block detection method with three major steps. In specific, we first analyze the format of the bitstream to obtain the mapping relationship between the configuration bits and configurable logic blocks because of the discontinuity of the configuration bits in the bitstream for one element. In order to reap the maturity of object detection techniques based on deep learning, our next step is to convert an FPGA bitstream to an image, following the proposed transformation method that takes account of both the adjacency nature of the programmable logic and the high degree of redundancy of configuration information. Once the image is obtained, a deep learning-based object detection algorithm is applied to this transformed image, and the objects detected can be reflected back to determine the function blocks of the original FPGA design. The deep neural network used for function block detection is trained and validated with a specially crafted bitstream/image dataset. Experiments have confirmed high detection accuracy of the proposed function detection method, showing a 98.11% of mean Average Precision (IoU = 0.5) for 10 function blocks within a YOLOv3 detector implemented on Xilinx Zynq-7000 SoCs and Zynq UltraScale+ MPSoCs.

关键词： field programmable gate arrays Deep learning Signal processing algorithms Logic gates Feature extraction Tools array signal processing Bitstream-to-image transformation field-programmable gate array function block detection

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