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Power Quality Disturbance Tracking Based on a Proprietary FPGA Sensor with GPS Synchronization

SENSORS 2021年第11期21卷 3910-3910页

作者： Pardo-Zamora, Oscar N. Romero-Troncoso, Rene de J. Millan-Almaraz, Jesus R. Morinigo-Sotelo, Daniel Osornio-Rios, Roque A. Antonino-Daviu, Jose A. Autonomous Univ Queretaro Fac Engn San Juan De Rio 76806 Mexico Autonomous Univ Sinaloa Fac Phys & Math Sci Culiacan 80040 Sinaloa Mexico Univ Valladolid Dept Elect Engn Valladolid 47011 Spain Univ Politecn Valencia Inst Tecnol Energia Valencia 46022 Spain

The study of power quality (PQ) has gained relevance over the years due to the increase in non-linear loads connected to the grid. Therefore, it is important to study the propagation of power quality disturbances (PQDs) to determine the propagation points in the grid, and their source of generation. Some papers in the state of the art perform the analysis of punctual measurements of a limited number of PQDs, some of them using high-cost commercial equipment. The proposed method is based upon a developed proprietary system, composed of a data logger FPGA with GPS, that allows the performance of synchronized measurements merged with the full parameterized PQD model, allowing the detection and tracking of disturbances propagating through the grid using wavelet transform (WT), fast Fourier transform (FFT), Hilbert-Huang transform (HHT), genetic algorithms (GAs), and particle swarm optimization (PSO). Measurements have been performed in an industrial installation, detecting the propagation of three PQDs: impulsive transients propagated at two locations in the grid, voltage fluctuation, and harmonic content propagated to all the locations. The results obtained show that the low-cost system and the developed methodology allow the detection of several PQDs, and track their propagation within a grid with 100% accuracy.

关键词： global positioning system industrial facilities propagation power quality disturbance particle swarm optimization genetic algorithms field-programmable gate array

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Gaussian random number generator: Implemented in FPGA for quantum key distribution

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND fieldS 2019年第3期32卷 e2554-e2554页

作者： Hu, Yue Wu, Yan Chen, Yi Wan, Guo Chun Tong, Mei Song Tongji Univ Coll Elect & Informat Engn Shanghai 201804 Peoples R China

Quantum key distribution is the process of using quantum communication to establish a shared key between two parties. It has been demonstrated the unconditional security and effective communication of quantum communication system can be guaranteed by an excellent Gaussian random number (GRN) generator with high speed and an extended random period. In this paper, we propose to construct the Gaussian random number generator by using field-programmable gate array (FPGA), which is able to process large data in high speed. We also compare three algorithms of GRN generation: Box-Muller algorithm, polarization decision algorithm, and central limit algorithm. We demonstrate that the polarization decision algorithm implemented in FPGA requires less computing resources and also produces a high-quality GRN through the null hypothesis test.

关键词： Gaussian random numbers quantum key distribution field-programmable gate array numerical modeling

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Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

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SENSORS 2024年第6期24卷 1891页

作者： Kang, Soongyu Lee, Seongjoo Jung, Yunho Korea Aerosp Univ Sch Elect & Informat Engn Goyang 10540 South Korea Sejong Univ Dept Elect Engn Seoul 05006 South Korea Sejong Univ Dept Convergence Engn Intelligent Drone Seoul 05006 South Korea Korea Aerosp Univ Dept Smart Air Mobil Goyang 10540 South Korea

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical-star (H-star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

关键词： field-programmable gate array internet of things network-on-chip restricted coulomb energy neural network

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Si APD-Based High Speed Infrared Radiation Thermometry for Analysing the Temperature Instability of a Combustion Chamber

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SENSORS 2024年第23期24卷 7780页

作者： Karapateas, Louis Lai, Yufeng Meng, Xiangfei Zhang, Yang Willmott, Jon R. Hobbs, Matthew J. Univ Sheffield Portobello Ctr Sch Elect & Elect Engn Sensor Syst Grp Pitt St Sheffield S14 ET England Univ Sheffield Sch Mech Aerosp & Civil Engn Sir Frederick Mappin BldgMappin St Sheffield S1 3JD England

This study introduces a novel approach to analysing the combustion process using a high-speed, non-contact, optical fibre-coupled Si avalanche photodiode (APD)-based infrared radiation thermometer (IRT). The Si APD-IRT, combined with an optimised field-programmable gate array (FPGA)-based digital design, achieves a response time of 1 mu s, faster than commercially available instruments. Our instrument captures the entire ignition and reignition cycle of a Jet A kerosene droplet with high temporal precision within a combustion chamber, a feat impossible with traditional thermocouples. The FPGA module was validated with a 1 mu s data acquisition time, using a 40 MHz onboard clock, achieving throughput of 0.64 Gbps with efficiencies of 0.062 Mbps/slice in lookup tables (LUTs), confirming a low-area design compared to conventional FPGAs. The IRT achieves a root mean square (RMS) noise specification of 0.5 degrees C at a 1 mu s acquisition time and a target temperature of approximately 1000 degrees C. A measurement uncertainty of within +/- 0.25% degrees C + 2 degrees C confirms that it lies within the bounds of commercial instrumentations. Our instrument was demonstrated to capture transient temperature fluctuations during combustion and characterises Jet A kerosene fuel droplets, laying the foundation for understanding sustainable aviation fuels (SAFs) and their role in transitioning from aviation fossil fuels, enabling effective research and development.

关键词： avalanche photodiode droplet combustion ignition infrared radiation thermometry field-programmable gate array

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FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

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ENERGIES 2024年第8期17卷 1870页

作者： Wu, Caiyun Zhang, Kai Zhang, Xin Shenyang Ligong Univ Sch Equipment Engn Shenyang 110159 Peoples R China Shenyang Ligong Univ Sch Automot & Transportat Shenyang 110159 Peoples R China

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional-integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

关键词： PMSM control system beetle antennae search field-programmable gate array intelligent optimization algorithm

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Design of a Low-Power Embedded System Based on a SoC-FPGA and the Honeybee Search Algorithm for Real-Time Video Tracking

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SENSORS 2022年第3期22卷 1280页

作者： Soubervielle-Montalvo, Carlos Perez-Cham, Oscar E. Puente, Cesar Gonzalez-Galvan, Emilio J. Olague, Gustavo Aguirre-Salado, Carlos A. Cuevas-Tello, Juan C. Ontanon-Garcia, Luis J. Univ Autonoma San Luis Potosi UASLP Fac Ingn Dr Manuel Nava 8Zona Univ Poniente San Luis Potosi 78290 San Luis Potosi Mexico Ctr Invest Cient & Educ Super Ensenada CICESE Carretera Ensenada Tijuana 3918Zona Playitas Ensenada 22860 Baja California Mexico Univ Autonoma San Luis Potosi UASLP Coordinac Acad Reg Altiplano Oeste Carretera Salinas Santo Domingo 200 San Luis Potosi 78600 San Luis Potosi Mexico

Video tracking involves detecting previously designated objects of interest within a sequence of image frames. It can be applied in robotics, unmanned vehicles, and automation, among other fields of interest. Video tracking is still regarded as an open problem due to a number of obstacles that still need to be overcome, including the need for high precision and real-time results, as well as portability and low-power demands. This work presents the design, implementation and assessment of a low-power embedded system based on an SoC-FPGA platform and the honeybee search algorithm (HSA) for real-time video tracking. HSA is a meta-heuristic that combines evolutionary computing and swarm intelligence techniques. Our findings demonstrated that the combination of SoC-FPGA and HSA reduced the consumption of computational resources, allowing real-time multiprocessing without a reduction in precision, and with the advantage of lower power consumption, which enabled portability. A starker difference was observed when measuring the power consumption. The proposed SoC-FPGA system consumed about 5 Watts, whereas the CPU-GPU system required more than 200 Watts. A general recommendation obtained from this research is to use SoC-FPGA over CPU-GPU to work with meta-heuristics in computer vision applications when an embedded solution is required.

关键词： heterogeneous computing meta-heuristic video tracking system-on-chip field-programmable gate array evolutionary computing swarm intelligence embedded system design graphics processing unit computer vision

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Miniaturization Design of High-Integration Unmanned Aerial Vehicle-Borne Video Synthetic Aperture Radar Real-Time Imaging Processing Component

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REMOTE SENSING 2024年第7期16卷 1273页

作者： Yang, Tao Wang, Tong Zheng, Nannan Zhang, Shuangxi Meng, Fanteng Zhang, Xinyu Wu, Qirui Xidian Univ Sch Aerosp Sci & Technol Xian 710126 Peoples R China Northwestern Polytech Univ Sch Elect & Informat Xian 710129 Peoples R China

The unmanned aerial vehicle (UAV)-borne video synthetic aperture radar (SAR) possesses the characteristic of having high-continuous-frame-rate imaging, which is conducive to the real-time monitoring of ground-moving targets. The real-time imaging-processing system for UAV-borne video SAR (ViSAR) requires miniaturization, low power consumption, high frame rate, and high-resolution imaging. In order to achieve high-frame-rate real-time imaging on limited payload-carrying platforms, this study proposes a miniaturization design of a high-integration UAV-borne ViSAR real-time imaging-processing component (MRIPC). The proposed design integrates functions such as broadband signal generation, high-speed real-time sampling, and real-time SAR imaging processing on a single-chip FPGA. The parallel access mechanism using multiple sets of high-speed data buffers increases the data access throughput and solves the problem of data access bandwidth. The range-Doppler (RD) algorithm and map-drift (MD) algorithm are optimized using parallel multiplexing, achieving a balance between computing speed and hardware resources. The test results have verified that our proposed component is effective for the real-time processing of 2048 x 2048 single-precision floating-point data points to realize a 5 Hz imaging frame rate and 0.15 m imaging resolution, satisfying the requirements of real-time ViSAR-imaging processing.

关键词： video synthetic aperture radar real-time imaging field-programmable gate array range-Doppler algorithm map-drift algorithm

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Two-tone distortion products in hardware-efficient cochlea model based on asynchronous cellular automaton oscillator

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IEICE ELECTRONICS EXPRESS 2021年第18期18卷 20210310-20210310页

作者： Takeda, Kentaro Torikai, Hiroyuki Hosei Univ Grad Sch Sci & Engn 3-7-2 Kajino Sho Koganei Tokyo 1848584 Japan

In this paper, we present a cochlea model whose nonlinear dynamics are described by an asynchronous cellular automaton. Our proposed model is demonstrated to enable the reproduction of two-tone distortion products. The proposed model is implemented on a field-programmable gate array (FPGA). It is subsequently demonstrated that our proposed model can be implemented using fewer hardware resources than a conventional cochlea model, which is a Hopf-type cochlea model, implemented on a digital signal processor performing a numerical integration.

关键词： cochlea field-programmable gate array Hopf oscillator asynchronous cellular automaton

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Design and implementation of an optical Gaussian noise generator

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OPTICAL ENGINEERING 2009年第8期48卷 085002-085002页

作者： Zao, Leonardo Loss, Gustavo Coelho, Rosangela Inst Militar Engn Dept Elect Engn Lab Res Commun & Opt Syst BR-22290 Rio De Janeiro Brazil

A design of a fast and accurate optical Gaussian noise generator is proposed and demonstrated. The noise sample generation is based on the Box-Muller algorithm. The functions implementation was performed on a high-speed Altera Stratix EP1S25 field-programmable gate array (FPGA) development kit. It enabled the generation of 150 million 16-bit noise samples per second. The Gaussian noise generator required only 7.4% of the FPGA logic elements, 1.2% of the RAM memory, 0.04% of the ROM memory, and a laser source. The optical pulses were generated by a laser source externally modulated by the data bit samples using the frequency-shift keying technique. The accuracy of the noise samples was evaluated for different sequences size and confidence intervals. The noise sample pattern was validated by the Bhattacharyya distance (Bd) and the autocorrelation function. The results showed that the proposed design of the optical Gaussian noise generator is very promising to evaluate the performance of optical communications channels with very low bit-error-rate values. (C) 2009 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3204156]

关键词： Gaussian noise optical noise generation field-programmable gate array FSK Bhattacharyya distance

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Parallelized Particle Swarm Optimization on FPGA for Realtime Ballistic Target Tracking

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SENSORS 2023年第20期23卷 8456-8456页

作者： Park, Juhyeon Lee, Heoncheol Kwon, Hyuck-Hoon Hwang, Yeji Choi, Wonseok Kumoh Natl Inst Technol Sch Elect Engn Gumi 39177 South Korea Kumoh Natl Inst Technol Dept IT Convergence Engn Gumi 39177 South Korea LIGNEX1 PGM R&D Lab Seongnam 13488 South Korea

This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general, particle swarm optimization requires a great deal of computation time, so it is difficult to apply to realtime systems. In this paper, we propose a parallelized particle swarm optimization technique using field-programmable gate array (FPGA) to be accelerated for realtime ballistic target tracking. The realtime performance of the proposed method has been tested and analyzed on a well-known heterogeneous processing system with a field-programmable gate array. The proposed parallelized particle swarm optimization was successfully conducted on the heterogeneous processing system and produced similar tracking results. Also, compared to conventional particle swarm optimization, which is based on the only central processing unit, the computation time is significantly reduced by up to 3.89x.

关键词： ballistic target tracking field-programmable gate array particle swarm optimization realtime system

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