This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the m...
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This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general, particle swarm optimization requires a great deal of computation time, so it is difficult to apply to realtime systems. In this paper, we propose a parallelized particle swarm optimization technique using field-programmable gate array (FPGA) to be accelerated for realtime ballistic target tracking. The realtime performance of the proposed method has been tested and analyzed on a well-known heterogeneous processing system with a field-programmable gate array. The proposed parallelized particle swarm optimization was successfully conducted on the heterogeneous processing system and produced similar tracking results. Also, compared to conventional particle swarm optimization, which is based on the only central processing unit, the computation time is significantly reduced by up to 3.89x.
A design of a fast and accurate optical Gaussian noise generator is proposed and demonstrated. The noise sample generation is based on the Box-Muller algorithm. The functions implementation was performed on a high-spe...
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A design of a fast and accurate optical Gaussian noise generator is proposed and demonstrated. The noise sample generation is based on the Box-Muller algorithm. The functions implementation was performed on a high-speed Altera Stratix EP1S25 field-programmable gate array (FPGA) development kit. It enabled the generation of 150 million 16-bit noise samples per second. The Gaussian noise generator required only 7.4% of the FPGA logic elements, 1.2% of the RAM memory, 0.04% of the ROM memory, and a laser source. The optical pulses were generated by a laser source externally modulated by the data bit samples using the frequency-shift keying technique. The accuracy of the noise samples was evaluated for different sequences size and confidence intervals. The noise sample pattern was validated by the Bhattacharyya distance (Bd) and the autocorrelation function. The results showed that the proposed design of the optical Gaussian noise generator is very promising to evaluate the performance of optical communications channels with very low bit-error-rate values. (C) 2009 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3204156]
In this paper, a portable assistance system is designed to help the visually impaired to detect the traffic light. The designed system is realized on the basis of the AdaBoost algorithm, which is fast and robust in ob...
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In this paper, a portable assistance system is designed to help the visually impaired to detect the traffic light. The designed system is realized on the basis of the AdaBoost algorithm, which is fast and robust in object detections. In order to accelerate the AdaBoost-based approach, a flexible parallel architecture is implemented on the field-programmable gate array (FPGA) platform. The architecture is designed utilizing the parallelism of computations in the AdaBoost-based detection. The computations of the window integral image are implemented in parallel, and the confidences of the weak classifiers are calculated in parallel. The parameters of the weak classifiers are trained by the AdaBoost algorithm with multi-layer features in the MATLAB software, and then are configured on the FPGA platform via the Vivado design suite before the detection process. The parallelism optimized architecture is implemented on an Artix-7 FPGA at 200 MHZ. Experiments show that it can detect the traffic light in videos with a rate of 30 frames per second (fps).
This paper presents an intelligent motion controller for four-wheeled holonomic mobile robots with four driving omnidirectional wheels equally spaced at 90 degrees from one another by using field-programmablegate arr...
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This paper presents an intelligent motion controller for four-wheeled holonomic mobile robots with four driving omnidirectional wheels equally spaced at 90 degrees from one another by using field-programmable gate array (FPGA)-based artificial immune system (AIS) algorithm. Both the nature-inspired AIS computational approach and motion controller are implemented in one FPGA chip to address the optimal control problem of real-world mobile robotics application. The proposed FPGA-based AIS method takes the advantages of artificial intelligence and FPGA technology by using system-on-a-programmable chip (SoPC) methodology. Experimental results are conducted to show the effectiveness and merit of the proposed FPGA-based AIS intelligent motion controller for four-wheeled omnidirectional mobile robots. This FPGA-based AIS autotuning intelligent controller outperforms the conventional nonoptimal controllers, the genetic algorithm (GA) controller, and the particle swarm optimization (PSO) controller.
Most of market-available logic analyzers are designed for hardware debug purposes and cannot record continuous measurement in long-term while in different fields of scientific research it is necessary to make data acq...
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Most of market-available logic analyzers are designed for hardware debug purposes and cannot record continuous measurement in long-term while in different fields of scientific research it is necessary to make data acquisition within small periods (less then 1 ms) during several hours or even days. The common example is real-time communication worst-case jitter analysis. This paper introduces an easy to implement approach how to create a logic analyzer for such kind of task on a basis of a low-cost field-programmable gate array (FPGA) kit and a personal computer. The Author provides both sample FPGA design files compatible with an open-source toolchain and the approach how to collect data using standard software and Octave scripts to post-process the experimental result. Following the Author's guidelines even with minimal knowledge in FPGA design makes it easy to modify the introduced hardware for specific laboratory team needs. (C) 2020 The Author(s). Published by Elsevier Ltd.
An ultra-high-speed algorithm based on Histogram of Oriented Gradient (HOG) and Support Vector Machine (SVM) for hardware implementation at 10,000 frames per second (FPS) under complex backgrounds is proposed for obje...
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An ultra-high-speed algorithm based on Histogram of Oriented Gradient (HOG) and Support Vector Machine (SVM) for hardware implementation at 10,000 frames per second (FPS) under complex backgrounds is proposed for object detection. The algorithm is implemented on the field-programmable gate array (FPGA) in the high-speed-vision platform, in which 64 pixels are input per clock cycle. The high pixel parallelism of the vision platform limits its performance, as it is difficult to reduce the strides between detection windows below 16 pixels, thus introduce non-negligible deviation of object detection. In addition, limited by the transmission bandwidth, only one frame in every four frames can be transmitted to PC for post-processing, that is, 75% image information is wasted. To overcome the mentioned problem, a multi-frame information fusion model is proposed in this paper. Image data and synchronization signals are first regenerated according to image frame numbers. The maximum HOG feature value and corresponding coordinates of each frame are stored in the bottom of the image with that of adjacent frames'. The compensated ones will be obtained through information fusion with the confidence of continuous frames. Several experiments are conducted to demonstrate the performance of the proposed algorithm. As the evaluation result shows, the deviation is reduced with our proposed method compared with the existing one.
The main goal of the article is to present the concept of using a simulation environment when designing an advanced fibre -optic seismometer (FOS) using a field -programmablegatearray (FPGA) computing system. The fi...
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The main goal of the article is to present the concept of using a simulation environment when designing an advanced fibre -optic seismometer (FOS) using a field -programmablegatearray (FPGA) computing system. The first part of the article presents the advanced requirements regarding the FOS principle of operation, as well as the measurement method using a closedloop operation. The closed -loop control algorithm is developed using the high-level language C++ and then it is synthesised into an FPGA. The following part of the article describes the simulation environment developed to test the operation of the control algorithm. The environment includes a model of components of the measurement system, delays, and distortions in the signal processing path, and some of the measurement system surroundings. The article ends with a comparison of simulation data with measurements. The obtained results are consistent and prove correctness of the methodology adopted by the authors.
Nowadays, the demand for high-performance wireless sensor networks (WSN) is increasing, and its power requirement has threatened the survival of WSN. The routing methods cannot optimize power consumption. To improve t...
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Nowadays, the demand for high-performance wireless sensor networks (WSN) is increasing, and its power requirement has threatened the survival of WSN. The routing methods cannot optimize power consumption. To improve the power consumption, VLSI based power optimization technology is proposed in this article. Different elements in WSN, such as sensor nodes, modulation schemes, and package data transmission, influence energy usage. Following a WSN power study, it was discovered that lowering the energy usage of sensor networks is critical in WSN. In this manuscript, a power optimization model for wireless sensor networks (POM-WSN) is proposed. The proposed system shows how to build and execute a power-saving strategy for WSNs using a customized collaborative unit with parallel processing capabilities on FPGA (fieldprogrammablegatearray) and a smart power component. The customizable cooperation unit focuses on applying specialized hardware to customize Operating System speed and transfer it to a soft intel core. This device decreases the OS (Operating System) central processing unit (CPU) overhead associated with installing processor-based IoT (Internet of Things) devices. The smart power unit controls the soft CPU's clock and physical peripherals, putting them in the right state depending on the hardware requirements of the program (tasks) being executed. Furthermore, by taking the command signal from a collaborative custom unit, it is necessary to adjust the amplitude and current. The efficiency and energy usage of the FPGA-based energy saver approach for sensor nodes are compared to the energy usage of processor-based WSN nodes implementations. Using FPGA programmable architecture, the research seeks to build effective power-saving approaches for WSNs.
Only a few effective methods can detect internal defects and monitor the internal state of complex structural parts. On the basis of the principle of PET (positron emission computed tomography), a new measurement meth...
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Only a few effective methods can detect internal defects and monitor the internal state of complex structural parts. On the basis of the principle of PET (positron emission computed tomography), a new measurement method, using gamma photon to detect defects of an inner surface, is proposed. This method has the characteristics of strong penetration, anti-corrosion and anti-interference. With the aim of improving detection accuracy and imaging speed, this study also proposes image reconstruction algorithms, combining the classic FBP (filtered back projection) with MLEM (maximum likelihood expectation Maximization) algorithm. The proposed scheme can reduce the number of iterations required, when imaging, to achieve the same image quality. According to the operational demands of FPGAs (field-programmable gate array), a BPML (back projection maximum likelihood) algorithm is adapted to the structural characteristics of an FPGA, which makes it feasible to test the proposed algorithms therein. Furthermore, edge detection and defect recognition are conducted after reconstructing the inner image. The effectiveness and superiority of the algorithm are verified, and the performance of the FPGA is evaluated by the experiments.
In this research work, an Adaptive Multi-Scale Dual Attention Network with ZOA for Multi-Objective CHS with energy-aware routing in 6G wireless Communication (CHS-EAR-AM-SDAN-6G) is proposed to secure the data transmi...
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In this research work, an Adaptive Multi-Scale Dual Attention Network with ZOA for Multi-Objective CHS with energy-aware routing in 6G wireless Communication (CHS-EAR-AM-SDAN-6G) is proposed to secure the data transmission by selecting optimum cluster heads in the 6G Wireless Communication network. Initially, the nodes are gathered together to form a cluster using an Adaptive Multi-Scale Dual Attention Network (AM-SDAN). The Zebra Optimization Algorithm (ZOA) strategically selects Cluster Heads (CHs) in wireless networks based on a multi-objective fitness function (MoFF) that minimizes energy consumption while considering factors, like distance, delay, and traffic density. The path and minimum value of fitness are recognized as the routing path and statistics are promoted to the sink node through the cluster head. The proposed scheme has been applied in Python and productivity of the proposed method is predictable with the help of several performances they are energy consumption, detection rate, computational time, packet delivery rate, number of alive nodes, and security. The performance of the proposed CHS-EAR-AMSDAN-6G method attains 25.93%, 24.81%, and 23.38% of alive nodes, 24.45%, 26.71% and 21.32% lower packet delivery rate, 27.56%, 26.43%, and 28.61% low computational period, related with three current methods, such as Generative Adversarial Learning for ITM in 6G Wireless Communication Networks (CHS-EAR-GAL-ITM-6G), ML Algorithms for the Future 6G WCN (CHS-EAR-ML-6G), Energy Efficient Distributed Federated Learning to the 6G Wireless Communication Networks (CHS-EAR-EEDFL-6G), respectively.
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