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The 2021 ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Yuze Chi Licheng Guo Young-kyu Choi Jie Wang Jason Cong University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450382182

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of result (QoR) and short development cycle compared with the traditional register-transfer level (RTL) design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools support task-parallel programs, the productivity is greatly limited in the code development, correctness verification, and QoR tuning cycles, due to the poor programmability, restricted software simulation, and slow code generation, respectively. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA *** this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, universal software simulation, and fast code generation to overcome these limitations. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly accelerated by 3.2× and 6.8×, respectively.

关键词： high-level synthesis task-parallel program field-programmable gate array

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Elimination of the Background of Electron Microscope Images by Using FPGA

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ACTA CYBERNETICA 2013年第1期21卷 123-134页

作者： Fazekas, Adam Daimon, Hiroshi Matsuda, Hiroyuki Toth, Ladszlo Univ Debrecen Fac Informat Dept Informat Syst & Networks Kassai Ut 26 H-4028 Debrecen Hungary Nara Inst Sci & Technol Ikoma Nara 6300192 Japan

The purpose of our development is to design an FPGA based hardware acceleration system that is able to be used for analyzing photoemission electron microscope (PEEM) images or improving their quality. Even though a usual PEEM has an energy filter unit, which is able to eliminate certain disturbing signals, a post processing computation can also be useful to improve the image quality. Here we propose an FPGA based hardware acceleration system for the computation of a certain image background component. It has uniquely designed hardware modules that perform the computations in parallel, resulting in less calculation time. The system shown here is a prototype which was only used for testing and experimental purposes.

关键词： photoelectron spectra Shirley background field-programmable gate array hardware acceleration

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Emerging application domains: research challenges and opportunities for FPGAs 09

Emerging application domains: research challenges and opport...

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Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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ACPU-FPGAheterogeneous approach for biological sequence comparison using high-level synthesis

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2021年第4期33卷 e6007-e6007页

作者： Jorge, Carlos A. C. Nery, Alexandre S. Melo, Alba C. M. A. Goldman, Alfredo Univ Brasilia Dept Comp Sci Brasilia DF Brazil Univ Brasilia Dept Elect Engn Brasilia DF Brazil Univ Sao Paulo Inst Math & Stat Sao Paulo Brazil

This article presents a high-level synthesis implementation of the longest common subsequence (LCS) algorithm combined with a weighted-based scheduler for comparing biological sequences prioritizing energy consumption or execution time. The LCS algorithm has been thoroughly tailored using Vivado High-Level Synthesis tool, which is able to synthesize register transfer level (RTL) from high-level language descriptions, such as C/C++. Performance and energy consumption results were obtained with a CPU Intel Core i7-3770 CPU and an Alpha-Data ADM-PCIE-KU3 board that has a Xilinx Kintex UltraScale XCKU060 FPGA chip. We executed a batch of 20 comparisons of sequences on 10k, 20k, and 50k sizes. Our experiments showed that the energy consumption on the combined approach was significantly lower when compared to the CPU, achieving 75% energy reduction on 50k comparisons. We also used the tool proposed in this article to do a case study on Covid-19, with real SARS-CoV-2 sequences, comparing their LCS scores.

关键词： biological sequence comparison dynamic programming field-programmable gate array high-level synthesis longest common subsequence

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Design of Handheld Oscilloscope Based on FPGA and Dual A/D

Design of Handheld Oscilloscope Based on FPGA and Dual A/D

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2016 4th International Conference on Electrical&Electronics Engineering and Computer Science(ICEEECS 2016)

作者： Hu Yang Yuduo Wang School of Information & Communication Engineering Beijing Information Science & Technology Univerdity

ISBN: (纸本)9781510835429

Handheld oscilloscope because of its portability, wide application range and other characteristics, has drawn more and more attention in the engineering practice. Anolog-todigital conversion circuit plays an important role in the design of digital oscilloscope. It directly determines the maximum frequency of digital oscilloscope can be measured. This paper focuses on the analysis of three methods of improving the sampling rate, eventually adopts double anolog-to-digital converter sampling approach to the design of a handheld oscilloscope, sampling frequency can reach two times the maximum sampling frequency of anolog-to-digital converter, so as to improve the accuracy of frequency measurement range of oscilloscope and the waveform display, and without significant increase in cost and easy to realize. The oscilloscope with embedded processor STM32 as control core, using field-programmable gate array(FPGA) for data processing. The signal collected by automatic gain control, dual anolog-digital converter sampling,data cache, digitalto-anolog conversion process, displayed on the screen. At the same time,the oscilloscope realizes the functions of test signal's display, measurement and the corresponding parameter adjustment.

关键词： Handheld oscilloscope field-programmable gate array STM32 Double Anologto-Digital sampling Sampling frequency

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Transmission of Subcarrier Square Wave in Radio over Fiber Communication System Based on FPGA

Transmission of Subcarrier Square Wave in Radio over Fiber C...

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作者： Mao Xinrong Wang Leyi Kou Zhaofei Chen Rong Xi'an University of Science & Technology

To avoid the disadvantages of Radio over Fiber(RoF) communication system in optical domain modulation,subcarrier modulation in electrical domain using fieldprogrammable gate array(FPGA) is proposed to generate baseband subcarrier square *** the subcarrier signal is modulated to optical signal using optical fiber experimental box,which can be transmitted through optical *** waveform of the original square wave can be observed on the oscilloscope after the transmission through the optical fiber system with good *** experimental results show that subcarrier modulation can be done in electrical domain,which prove the feasibility of subcarrier modulation in the electrical domain using FPGA,and providing another way of subcarrier modulation.

关键词： Radio over Fiber Subcarrier Modulation Square Wave field-programmable gate array

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HARDWARE IMPLEMENTATION OF THE DISCRETE FOURIER TRANSFORM WITH NON-POWER-OF-TWO PROBLEM SIZE

HARDWARE IMPLEMENTATION OF THE DISCRETE FOURIER TRANSFORM WI...

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IEEE International Conference on Acoustics, Speech, and Signal Processing

作者： Peter A. Milder Franz Franchetti James C. Hoe Markus Puschel Carnegie Mellon University Department of Electrical and Computer Engineering Pittsburgh PA United States

ISBN: (纸本)9781424442959

In this paper, we examine several algorithms suitable for the hardware implementation of the discrete Fourier transform (DFT) with non-power-of two problem size. We incorporate these algorithms into Spiral, a tool capable of automatically generating corresponding hardware implementations. We discuss how each algorithm can be used to generate different types of hardware structures, and we demonstrate that our tool is able to produce hardware implementations of non-power-of-two sized DFTs over a wide range of cost/performance tradeoff points.

关键词： Discrete Fourier transform high-level synthesis field-programmable gate array FPGA algorithms

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Design of a Multichannel Time Interval Measurement Interface Box

Design of a Multichannel Time Interval Measurement Interface...

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作者： Don, M. L Pugh, K. E Kline, B. J Hallameyer, J. M CCDC Army Research Laboratory Aberdeen Proving Ground United States

Precise time interval measurement is required for a number of applications including clock stability analysis, time-of-flight measurements, and particle physics. Commercial time interval measurement devices can achieve picosecond resolution but are expensive, especially for multichannel applications. In previous research, the US Army Combat Capabilities Development Command Army Research Laboratory demonstrated 10-ns resolution on 10 channels using a low-cost field-programmable gate array (FPGA) suitable for pulse-per-second monitoring. This technical note details the design of an interface box for this FPGA device, enabling practical time interval measurement with a variety of input signals. The purpose of this note is twofold: 1) to document the interface box to allow for easy use and future modifications and 2) to provide a reference to facilitate the construction of other interface units, including design advice and lessons learned.

关键词： field programmable gate array Time intervals Measurement Monitoring Time interval measurement field-programmable gate array Pulse per second Test and measurement Electronic interface

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On-line Estimation of Power Battery SOC Based on FPGA

On-line Estimation of Power Battery SOC Based on FPGA

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2018 2nd International Conference on Modeling, Simulation and Optimization Technologies and Applications(MSOTA 2018)

作者： Xiao MA Qing TAO Wen-bing YIN Dan-feng QIU Jing-dong ZHANG Bin ZHAO Key Laboratory of Radar Imaging and Microwave Photonics (Nanjing Univ. Aeronaut. Astronaut.) Ministry of Education College of Electronic and Information Engineering Nanjing University of Aeronautics and Astronautics National Laboratory of Microstructures and School of Electronic Science and Engineering Nanjing University

Battery technology has been the bottleneck of the development of electric vehicle technology. In order to grasp the battery state in real time, it is becoming more and more important to design a battery management technology(BMS) that can monitor and adjust battery state in real time. SOC(State of charge) is an important parameter to describe the charge and discharge capacity of the battery. It is of great significance to give full play to the performance of the battery system, improve the safety of the battery, prevent the overcharge and discharge of the battery, and prolong the life of the battery. Therefore, BMS should be able to accurately estimate the SOC of battery in real time. This paper uses the method of OCV-AH to estimate the SOC of battery, and uses field-programmable gate array(FPGA) to realize this method from two aspects of hardware and software.

关键词： Battery management system State of charge field-programmable gate array

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Design and Realization of IF Digital Receiver

Design and Realization of IF Digital Receiver

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2012 International Conference on Environmental Engineering and Technology(ICEET2012)

作者： Wang Run-qi,Li Yi-hua College of Logistics,Central South University of Forestry and Technology Changsha,China

An intermediate frequency digital receiver based on FPGA is introduced in the *** scheme of system realization is proposed and the design of every hardware circuit is described in *** main function module in FPGA of the system is described with carefully and implementation result of every module is *** correctness of every main function module is verified by *** condition of no varying hardware platform,the system can realize different function and technical index by changing software program and have higher universality and practical value.

关键词： Digital receiver field-programmable gate array Low pass filter Digital quadrature mixing

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