检索结果-内蒙古大学图书馆

Optimized FFT Designs for High-Performance LTE and 5G Networks

ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING 2025年 1-20页

作者： Khan, Daud Jan, Latif Zafar, Mohammad Haseeb IQRA Natl Univ Dept Comp Sci Peshawar 25100 Khyber Pakhtunk Pakistan Cardiff Metropolitan Univ Cardiff Sch Technol Cardiff CF5 Wales

This paper proposes a run-time reconfigurable butterfly structure capable of simultaneously performing Radix-8, Radix-4, Radix-3, and Radix-2 Fast Fourier Transform (FFT) computations to cater to the bandwidth requirements of current Long-Term Evolution (LTE), Fifth Generation (5G), and beyond systems. While LTE and 5G promise exceptionally high throughput, ranging from 300 Mbps to 3 Gbps, field-programmable gate array (FPGA) and Application Specific Integrated Circuit vendors face significant challenges in meeting these demands. Efficient implementation strategies are essential for realizing these standards in silicon. Given that FFT is the cornerstone of 5G systems, its computational complexity poses challenges in meeting high throughput requirements. Furthermore, the flexibility to adapt to different bandwidths is crucial in 5G networks. Therefore, a configurable FFT engine that optimizes resource utilization while providing high throughput is highly desirable. This paper presents two FFT architectures based on the proposed reconfigurable butterfly, offering designers the flexibility to choose the most suitable approach for realizing efficient and high-throughput solutions tailored to the requirements of 5G and beyond.

关键词： Fast Fourier transform field-programmable gate array Application specific integrated circuit 5th generation Long-term evolution

来源：评论

学校读者我要写书评

暂无评论

Efficient Co-Approximate Parallel Compressive Depth Reconstruction on FPGA

Efficient Co-Approximate Parallel Compressive Depth Reconstr...

引用

2025 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Wu, Yun McAllister, John School of Electrical Electronic and Computer Engineering Queen's University Belfast United Kingdom

ISBN: (纸本)9798350368741

Efficient depth image reconstruction from sparse samples is crucial for machine perception applications, such as robotics, vehicle assistance and autonomy. It demands fast processing speed with low power consumption for sensing quality and safety, as well as cost reduction for FPGA and solid state implementations, within constrained resource budgets on edge devices. A new co-approximate framework of parallel approximate compressive depth reconstruction engine on FPGA is proposed using 1 solvers, proximal gradient decent (PGD), with instrumented frequency and voltage scaling during the iterative optimization process. By evaluating various number of parallel approximate processing units for the depth image reconstruction engine, up to 51% further power saving is achieved, and 421× speed up of parallel processing compared to the baseline, henceforth the efficiency is elevated over 43×. © 2025 IEEE.

关键词： Approximate Computing Compressive Sensing Convex Optimization Depth Reconstruction field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Optimized theory-guided convolutional neural network for lung cancer classification using CT images with advanced FPGA implementation

引用

BIOMEDICAL SIGNAL PROCESSING AND CONTROL 2025年 106卷

作者： Manikandan, S. Karthigaikumar, P. Karpagam Coll Engn Dept Elect & Telecommun Engn Coimbatore Tamil Nadu India Karpagam Coll Engn Dept Elect & Commun Engn Coimbatore Tamil Nadu India

Lung carcinoma, commonly referred to as lung cancer is a severe disease with higher global mortality rate. The uncontrolled growth of cells in lung tissues is the reason for it. Detecting and treating lung cancer early is important for curing it, and diagnostic methods commonly include Computed Tomography (CT) scans and blood tests. However, accurately detecting and classifying pulmonary nodules in CT images remains a challenge due to the complexity of the data, higher computational demands,require for real-time processing. Existing systems often face limitations, such as high power consumption, prolonged processing times, and scalability issues, reducing their effectiveness in clinical environments. To overcome these challenges, this manuscript proposes an Optimized Theory-Guided Convolutional Neural Network for Lung Cancer Classification utilizing CT Images with Advanced FPGA Implementation (OTCNN-LCT-FPGA). Computed Tomography Image (CTI) from the LIDC-IDRI dataset are pre-processed using Variational Bayesian Robust Adaptive Filtering (VBRAF) technique, which removes noise and converts RGB images into binary format. The pre-processed images are classified as benign or malignant using Theory-Guided Convolutional Neural Network (TCNN). The Polar Coordinate Bald Eagle Search Algorithm (PBESA) is introduced to enhance the weight parameters of TCNN method while reducing resource utilization and increasing processing speed. The TCNN classifier is executed on field-programmable gate array (FPGA) to further decrease the computation time. The proposed OTCNN-LCT-FPGA method demonstrates significant improvements. How if, it achieves 6.26 %, 7.22 %, and 5.27 higher specificity and 2.96 %, 3.46 %, and 5.80 % higher F1-Score when compared to the existing methods, such as FCFNN-LCC, ISNeT-DLC-CT and DNNLCC-EOS respectively.

关键词： CT images field-programmable gate array Lung cancer Variational based Bayesian robust Adaptive Filtering Polar Coordinate Bald Eagle Search Algorithm Theory-guided Convolutional Neural Network

来源：评论

学校读者我要写书评

暂无评论

Design and analysis of a dual mode CMOS field programmable analog array

引用

Journal of Semiconductors 2014年第10期35卷 152-162页

作者：程小燕杨海钢尹韬吴其松张洪锋刘飞 Institute of Electronics Chinese Academy of Sciences University of Chinese Academy of Sciences

This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.

关键词： field-programmable gate array field-programmable analog array configurable analog block rail-to- rail biquadratic filters

来源：评论

学校读者我要写书评

暂无评论

Research on Spaceborne Neural Network Accelerator and Its Fault Tolerance Design

引用

REMOTE SENSING 2025年第1期17卷 69-69页

作者： Shao, Yingzhao Wang, Junyi Han, Xiaodong Li, Yunsong Li, Yaolin Tao, Zhanpeng Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China China Acad Space Technol Xian Xian 710100 Peoples R China Xidian Univ Sch Comp Sci & Technol Xian 710071 Peoples R China

To meet the high-reliability requirements of real-time on-orbit tasks, this paper proposes a fault-tolerant reinforcement design method for spaceborne intelligent processing algorithms based on convolutional neural networks (CNNs). This method is built on a CNN accelerator using field-programmable gate array (FPGA) technology, analyzing the impact of Single-Event Upsets (SEUs) on neural network computation. The accelerator design integrates data validation, Triple Modular Redundancy (TMR), and other techniques, optimizing a partial fault-tolerant architecture based on SEU sensitivity. This fault-tolerant architecture analyzes the hardware accelerator, parameter storage, and actual computation, employing data validation to reinforce model parameters and spatial and temporal TMR to reinforce accelerator computations. Using the ResNet18 model, fault tolerance performance tests were conducted by simulating SEUs. Compared to the prototype network, this fault-tolerant design method increases tolerance to SEU error accumulation by five times while increasing resource consumption by less than 15%, making it more suitable for spaceborne on-orbit applications than traditional fault-tolerant design approaches.

关键词： spaceborne computing single-event upset convolutional neural network field-programmable gate array fault-tolerant design

来源：评论

学校读者我要写书评

暂无评论

Software and hardware synergy for accelerated plant disease identification

引用

APPLIED SOFT COMPUTING 2025年 174卷

作者： Wen, Hongxing Li, Chuandong Wang, Xinpei Chen, Ling Southwest Univ Coll Elect Informat & Engn Chongqing Key Lab Nonlinear Circuits & Intelligent Chongqing 400715 Peoples R China

Plant diseases are one of the main causes of reduced crop yields. Therefore, it is necessary to adopt timely and effective identification methods and take corresponding measures. Some physical and biological detection methods have been proposed by researchers, but these methods require specialized techniques and expensive detection costs. Furthermore, the limited number of skilled technicians means that disease identification is not always timely or effective. To achieve real-time identification of plant diseases in remote areas where network and circuit are not well connected, We adopted a hardware and software co-acceleration approach to implement the design. First, we designed a lightweight convolutional neural network (CNN) and trained this network using a knowledge distillation approach. Then, we quantified the model parameters into int8 type using a method of model quantization to further compress the model size. After compression, the model size of the network is 0.035 MB and the recognition accuracy is 94.06% on the test set of the experiment. In order to deploy the proposed network on resource constrained field-programmable gate array (FPGA) devices, we used time-division multiplexing and feature map segmentation to deploy the network. Finally, our design is implemented on ZYNQ7020 with an inference speed of 35.73ms/frame and a power consumption of 1.97 W. The experimental results show that our design has the advantages of consuming less FPGA resources, low power consumption, high speed and portability. It can be used for disease recognition in multiple plant classes.

关键词： Convolutional neural network field-programmable gate array Acceleration Plant disease

来源：评论

学校读者我要写书评

暂无评论

Design of an FPGA-based emulator for rapidly prototyping a nonvolatile system-on-a-chip

引用

JAPANESE JOURNAL OF APPLIED PHYSICS 2025年第4期64卷 04SP06-04SP06页

作者： Suzuki, Daisuke Hanyu, Takahiro Univ Aizu 90 Kami IawaseTsurugaIkki Machi Aizu Wakamatsu Fukushima 9658580 Japan Tohoku Univ 2-1-1 KatahiraAoba Ku Sendai Miyagi 9808577 Japan

This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.

关键词： field-programmable gate array nonvolatile logic hardware emulation system on a chip prototyping

来源：评论

学校读者我要写书评

暂无评论

Wearable sensor-based measurement and classification of athletic activities using FPGA and EdgeTPU

引用

PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART P-JOURNAL OF SPORTS ENGINEERING AND TECHNOLOGY 2025年

作者： Muralikrishnan, P. Maheswari, M. K Ramakrishnan Coll Engn Samayapuram Kariyamanickam Rd Tiruchirappalli 621112 Tamil Nadu India

Wearable sensors, such as smartwatches, often face challenges in providing accurate readings due to variations in sensor quality and placement irregularities. Furthermore, deep convolutional neural networks (CNNs) can be resource-intensive, making them less suitable for real-time applications in wearable technology. This study introduces a novel approach utilizing Edge Tensor Processing Units (EdgeTPUs) combined with field-programmable gate arrays (FPGAs) for activity classification in athletes, specifically designed for resource-constrained environments. EdgeTPU models are optimized for low memory usage and high computational efficiency, making them ideal for microcontrollers used in wearable devices. To address model size and complexity, we employ quantization techniques and a lightweight neural network design. Experiments using the UCI-HAR, WISDM, and WEAR datasets show that our approach achieves a classification accuracy of 98.97%. The FPGA implementation offers high throughput and low latency, critical for real-time processing in wearable sensors. Additionally, we present three innovative approaches for complex loop optimization to enhance convolution efficiency. With a usage rate of 24.6%, the EdgeTPU model implemented on a Virtex-7 FPGA demonstrates effective hardware utilization. Our results indicate that the integration of FPGA and EdgeTPU technologies enables efficient real-time monitoring of athletic activities in wearable devices with limited resources.

关键词： Edge tensor processing unit athletic activities field-programmable gate array FPGA implementation signal classification

来源：评论

学校读者我要写书评

暂无评论

Multiscroll hopfield neural network with extreme multistability and its application in video encryption for IIoT

引用

NEURAL NETWORKS 2025年 182卷 106904页

作者： Yu, Fei Lin, Yue Yao, Wei Cai, Shuo Lin, Hairong Li, Yi Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Peoples R China Cent South Univ Sch Elect Informat Changsha 410083 Peoples R China Hunan Post & Telecommun Planning & Designing Inst Changsha 410126 Peoples R China

In Industrial Internet of Things (IIoT) production and operation processes, a substantial amount of video data is generated, often containing sensitive personal and commercial information. This paper proposed three new multiscroll Hopfield neural network (MHNN) systems by utilizing an improved segmented nonlinear non- ideal magnetic-controlled memristor model for electromagnetic radiation. Through dynamical methods, the constructed neural network's multidimensional multiscroll attractors and initial offset boosting behavior are analyzed. The observed initial offset boosting behavior demonstrates the system has extreme multistability. Secondly, a video encryption application based on the MHNN system is implemented on the Raspberry Pi platform. This approach encrypts each frame of the extracted video image using a novel encryption algorithm through frame-by-frame encryption, achieving significant encryption results with an information entropy calculation result of 7.9973. This provides strong protection for video data generated in IIoT. Finally, the proposed MHNN system is implemented on field-programmable gate array (FPGA) digital hardware platform.

关键词： Industrial internet of things Video encryption Multiscroll hopfield neural network Extreme multistability field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on field-programmable gate arrays

引用

IEEE TRANSACTIONS ON RELIABILITY 2013年第1期62卷 13-22页

作者： Aliee, Hananeh Zarandi, Hamid Reza Amirkabir Univ Technol Tehran Polytech Dept Comp Engn & Informat Technol Tehran 15914 Iran

This paper presents a method based on stochastic logic to analyse fault trees. This method supports both static and dynamic gates, and can be applied to any type of fault trees. In this paper, static and dynamic gates would be translated into stochastic logic templates, and a hardware implementation for each gate would be achieved. Based on these hardware templates, it is possible to implement the whole logic on a field-programmable gate array (FPGA). Utilizing the stochastic logic for implementing a given fault tree on FPGA, the analysis would outperform the following parameters compared to traditional methods: 1) Speed-up, 2) Simplicity, 3) Reliability, and 4) Accuracy. Experimental results illustrate that using stochastic logic for modeling fault trees results in fast convergence of Monte Carlo simulation. Moreover, on average, our FPGA approach takes 50% of the time required by previous emulation approaches. Simplicity is an additional advantage of the proposed approach, achieved because of simplicity behind stochastic logic. Also, the stochastic logic is more reliable compared to traditional logic because any faults like SEUs in stochastic logic have less impact on the whole results compared to traditional arithmetic logic. To evaluate the proposed technique, the analysis is performed on several standard benchmarks composed of static and dynamic gates. The results obtained using this approach agree with those obtained from an analytical approach, which proves that the method is an accurate tool for system reliability modeling.

关键词： Fault tree analysis field-programmable gate array single event upset static and dynamic gates stochastic logic

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：