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EFFICIENT DIGITAL IMPLEMENTATION OF SIGNAL PROCESSING ALGORITHMS IN STATE-OF-THE-ART field-programmable gate arrayS FOR GAMMA-RAY SPECTROSCOPY

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NUCLEAR TECHNOLOGY 2014年第1期187卷 69-81页

作者： Fahiman, Fateme Kafaee, Mahdi Moussavi-Zarandi, Alt Fahiman, Meisam Amirkabir Univ Technol Dept Energy Engn & Phys Tehran Iran Iran Univ Sci & Technol Dept Comp Engn Tehran Iran

In this work, a board based on a Spartan-3 field-programmable gate array was designed as a hardware prototyping platform for development of a multichannel digital gamma spectrometer. The device is compatible with various detectors like high-purity germanium, NaI, and CsI detectors. Before implementing the hardware, the method for digital signal processing for gamma spectroscopy was developed. The aim of this paper is to introduce a robust tool suitable for optimizing the design of complicated systems. The characteristics of this method, such as its ability to implement adaptive shaping, are investigated. The optimum conditions for digital filtering were determined using MATLAB/Simulink. This scheme can be useful for commercial production. Simulation was used to examine each processing unit in the whole signal processing procedure including cusplike shaping. The proposed method can be used as a computer design tool for optimizing digital multichannel analyzers or digital nuclear spectrometers.

关键词： digital pulse spectrometer system simulation field-programmable gate array

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Single and multiple precision sequential large multipliers for field-programmable gate arrays

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第4期24卷 2961-2973页

作者： Senturk, Ali Gok, Mustafa Cukurova Univ Dept Comp Engn Adana Turkey Cukurova Univ Dept Elect Engn Adana Turkey

This paper presents single and multiple precision sequential large multiplier designs for field-programmable gate arrays. Both designs use the Karatsuba Ofman method. They are pipelined and can generate a full size (double operand size) or a single size product. The syntheses results show that the sequential large Karatsuba Ofman multiplier (SLKOM) implementations have up to 2.23 times less delay compared with the standard sequential large multipliers implementations presented in previous research. The 2048-bit multiple precision sequential Karatsuba Ofman large multiplier (MPSLKOM) implementation can simultaneously execute eight 256-bit multiplications. The MPSLKOM implementations use roughly 1% more registers and up to 3% more LUTs than the SLKOM implementations.

关键词： Large multipliers Karatsuba-Ofman field-programmable gate array

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Design and Xilinx Virtex-fieldprogrammable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2023年第5期237卷 839-869页

作者： Krim, Saber Mimouni, Mohamed Faouzi Univ Kairouan Higher Inst Appl Sci & Technol Kasserine Kairouan Tunisia Univ Monastir Natl Engn Sch Monastir Lab Automat Elect Syst & Environm Monastir Tunisia Univ Kairouan Higher Inst Appl Sci & Technol Kasserine Kairouan 3100 Tunisia

This article aims first to propose an improved space vector modulation-direct torque control in order to enhance the induction motor performance using: (1) a super-twisting controller and (2) a novel model reference adaptive system based on a sliding mode observer. Second, due to the complexity of the suggested control algorithm, this article deals also with a hardware implementation on a field-programmable gate array board. Indeed, the field-programmable gate array is mainly chosen to reduce the execution time, thanks to its parallel processing which significantly improves the quality of the control system by reducing the sampling period, and consequently the delays in the control loop. Besides, the super-twisting controller is proposed to enhance the speed regulation loop which is a second-order sliding mode control technique that uses a continuous control law to prevent the chattering phenomenon induced by the first-order sliding mode control technique. Moreover, the high performance control requires information about the rotor speed which can be obtained by a sensor. Generally, the use of the speed sensor increases the system cost and size, and reduces its system reliability. Therefore, a combination between a model reference adaptive system observer and a sliding mode observer is suggested for speed estimation and overcoming the sensitivity of the classical model reference adaptive system observer against uncertainties and stator resistance variations. The performance of the proposed space vector modulation-direct torque control-super-twisting controller with the model reference adaptive system-sliding mode observer algorithm of an induction motor is verified through simulation, hardware co-simulation and experimental validation utilizing a field-programmable gate array Virtex-5-ML507 board. The performance of the suggested sensorless control method is compared also with other recent published schemes.

关键词： field-programmable gate array Xilinx system generator hardware architecture induction motor super-twisting model reference adaptive system

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Spaceborne synthetic aperture radar signal processing using field-programmable gate arrays

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JOURNAL OF APPLIED REMOTE SENSING 2018年第3期12卷

作者： Sugimoto, Yohei Ozawa, Satoru Inaba, Noriyasu Japan Aerosp Explorat Agcy Res & Dev Directorate Tsukuba Ibaraki Japan

Synthetic aperture radar (SAR) imagery requires image reproduction through the successive signal processing of received data before browsing images and extracting information. The received signal data records of ALOS-2/PALSAR-2 are stored in the onboard mission data storage and transmitted to the ground. To compensate for storage usage and transmission data capacity through the mission data communication network, the operation duty of PALSAR-2 is limited. This balance strongly relies on network availability. The observation operations of current spaceborne SAR systems are rigorously planned by simulating the mission data balance, given conflicting user demands. This problem should be solved so that we need not compromise the operations and potential of next-generation spaceborne SAR systems. One of the solutions is to compress the SAR data through onboard image reproduction and information extraction from the reproduced images. This is also beneficial for fast delivery of information products and event-driven observations by constellation. The Emergence Studio (Sohatsu kobo in Japanese) of the Japan Aerospace Exploration Agency has been developing evaluation models of the image processing system with the field-programmable gate array for onboard SAR image reproduction. The first model called the "Fast L1 Processor (FLIP)" can reproduce a 10-m resolution, single-look complex image (level 1.1) from ALOS/PALSAR raw signal data (level 1.0). FLIP processing speed at 200 MHz results in processing about five times faster than CPU-based computing at 3.7 GHz, corresponding to 50% real-time processing capability for ALOS/PALSAR. The FLIP'S image is almost identical to the image reproduced by 32-bit simulation in MATLAB. (C) 2018 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： synthetic aperture radar image reproduction onboard processing real-time processing field-programmable gate array

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Are field-programmable gate arrays Ready for the Mainstream?

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IEEE MICRO 2011年第6期31卷 58-63页

作者： Stitt, Greg Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

Although field-programmable gate arrays (FPGAs) can offer a significant performance advantage over alternate devices, they remain a niche technology. This column addresses the barriers to widespread FPGA use and explo... 详细信息

关键词： Adders Computer architecture field programmable gate arrays field-programmable gate array FPGA GPU Graphics processing unit multicore Parallel processing

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Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Controller Design with Resistive Random-Access Memories (RRAM) for field-programmable gate arrays (FPGA)

Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Cont...

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IEEE Regional Symposium on Micro and Nanoelectronics (IEEE-RSM)

作者： Chee, Hock Leong Kumar, T. Nandha Almurib, Haider A. F. Kang, Desmond Wen Hui Univ Nottingham Dept Elect & Elect Engn Semenyih Selangor Malaysia

ISBN: (纸本)9781728104607

This paper studies the simulation results of a novel controller circuit design for non-volatile (NV) look-up tables (LUT) combined with an electrical model of a resistive random-access memory (RRAM)-an emerging non-volatile memory (NVM) device. The Write and Read schemes of the controller is tested for a 2x2 RRAM array. The selected RRAM successfully switches between low '0' and high '1' while the unselected the RRAM remain undisturbed, demonstrating the elimination of the intrinsic sneak-path current problem in RRAMs. Reading of a selected RRAM is also performed with agreeable results.

关键词： field-programmable gate array memristor non-volatile look-up table non-volatile memory resistive random-access memory resistive switching

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Loop Unrolling for Energy Efficiency in Low-Cost field-programmable gate arrays

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2019年第4期11卷 26-26页

作者： Dumpala, Naveen Kumar Patil, Shivukumar B. Holcomb, Daniel Tessier, Russell Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

field-programmable gate arrays (FPGAs) are used for a wide variety of computations in low-cost embedded systems. Although these systems often have modest performance constraints, their energy consumption must typically be limited. Many FPGA applications employ repetitive loops that cannot be straightforwardly split into parallel computations. Performing a loop sequentially generally requires high-speed clocks that consume considerable clock power and sometimes require clock generation using a phase-locked loop (PLL). Loop unrolling addresses the high-speed clock issue, but its use often leads to significant combinational glitch power. In this work, a computer-aided design (CAD) approach that unrolls loops for designs targeted to low-cost FPGAs is described. Our approach considers latency constraints in an effort to minimize energy consumption for loop-based computation. To reduce glitch power, a glitch-filtering approach is introduced that provides a balance between glitch reduction and design performance. Glitch-filter enable signals are generated and routed to the filters using resources best suited to the target FPGA. Our approach automatically inserts glitch filters and associated control logic into a design prior to processing with FPGA synthesis, place, and route tools. Our energy-saving loop-unrolling approach has been evaluated using five benchmarks often used in low-cost FPGAs. The energy-saving capabilities of the approach have been evaluated for an Intel Cyclone IV and a Xilinx Artix-7 FPGA using board-level power measurement. The use of unrolling and glitch filtering is shown to reduce energy by at least 65% for an Artix-7 device and 50% for a Cyclone IV device while meeting design latency constraints.

关键词： field-programmable gate array loop unrolling energy

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Optimum and heuristic synthesis of multiple word-length Architectures

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2005年第1期13卷 39-57页

作者： Constantinides, GA Cheung, PYK Luk, W Univ London Imperial Coll Sci Technol & Med Dept Elect Engn London SW7 2BT England Univ London Imperial Coll Sci Technol & Med Dept Chem London SW7 2BZ England

This paper explores the problem of architectural synthesis (scheduling, allocation, and binding) for multiple word-length systems. It is demonstrated that the resource allocation and binding problem, and the interaction between scheduling, allocation, and binding, are complicated by the existence of multiple word-length operators. Both optimum and heuristic approaches to the combined problem are formulated. The optimum solution involves modeling as an integer linear program, while the heuristic solution considers intertwined scheduling, binding, and resource word-length selection. Techniques are introduced to perform scheduling with incomplete word-length information, to combine binding and word-length selection, and to refine word-length information based on critical path analysis. Results are presented for several benchmark and artificial examples, demonstrating significant resource savings of up to 46% are possible by considering these problems within the proposed unified framework.

关键词： binding bitwidth digital signal processing field-programmable gate array high-level synthesis scheduling word-length

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Operation method for parallel inverter system with common dc link

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IET POWER ELECTRONICS 2014年第5期7卷 1138-1147页

作者： Song, Chunwei Zhao, Rongxiang Zhu, Minglei Zeng, Zheng Zhejiang Univ Dept Elect Engn Hangzhou 310027 Peoples R China

The configuration of parallel inverter system (PIS) with common dc link and no isolation measure is proposed. The gate control signals for switches in parallel inverters are synchronised to achieve ideal parallel operation status. Adopting the double loop control method which is composed of an outer voltage loop and an inner current loop, PIS has good dynamic response and robustness. In addition, the circulating current caused by the delay time of control signal transmission is studied in detail. The proposed operation method is easy to be implemented on the digital control board using digital signal processing and field-programmable gate array. The simulation and experimental results are presented to demonstrate the validity and features of the proposed operation method.

关键词： dynamic response electric current control invertors synchronisation voltage control parallel inverter system common dc link PIS gate control signal transmission switches double loop control method outer voltage control loop inner current control loop dynamic response circulating current delay time digital control board digital signal processing field-programmable gate array

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FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

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MICROPROCESSORS AND MICROSYSTEMS 2007年第5期31卷 313-325页

作者： Zemva, Andrej Verderber, Matjaz Univ Ljubljana Fac Elect Engn Ljubljana 1000 Slovenia

This paper presents an FPGA-oriented implementation methodology for the MPEG-4 video decoder based on a hardware/software co-design approach. The MPEG-4 decoder is based on MoMuSys optimized reference software combined with new hardware VLSI architectures. New architectures for input demultiplexing, variable length decoding and inverse discrete cosine transform are developed. All software and hardware structures are evaluated in terms of visual quality, computational complexity and memory bandwidth metrics. The presented implementation is compared with an optimized reference software-based solution. Simulation results demonstrate a reduction of decoder complexity, especially speed and memory bandwidth, while maintaining an acceptable quality of decoded sequences. The proposed hardware additions provide 30% speed improvement over software solution, thereby reducing the clock rate required to process full-rate video from 300 MHz down to 213 MHz. The MPEG-4 decoder was functionally tested on a Flextronics FPGA prototyping board. (c) 2006 Elsevier B.V. All rights reserved.

关键词： MPEG-4 decoder field-programmable gate array hardware very large scale integration co-design

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