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FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

MICROPROCESSORS AND MICROSYSTEMS 2007年第5期31卷 313-325页

作者： Zemva, Andrej Verderber, Matjaz Univ Ljubljana Fac Elect Engn Ljubljana 1000 Slovenia

This paper presents an FPGA-oriented implementation methodology for the MPEG-4 video decoder based on a hardware/software co-design approach. The MPEG-4 decoder is based on MoMuSys optimized reference software combined with new hardware VLSI architectures. New architectures for input demultiplexing, variable length decoding and inverse discrete cosine transform are developed. All software and hardware structures are evaluated in terms of visual quality, computational complexity and memory bandwidth metrics. The presented implementation is compared with an optimized reference software-based solution. Simulation results demonstrate a reduction of decoder complexity, especially speed and memory bandwidth, while maintaining an acceptable quality of decoded sequences. The proposed hardware additions provide 30% speed improvement over software solution, thereby reducing the clock rate required to process full-rate video from 300 MHz down to 213 MHz. The MPEG-4 decoder was functionally tested on a Flextronics FPGA prototyping board. (c) 2006 Elsevier B.V. All rights reserved.

关键词： MPEG-4 decoder field-programmable gate array hardware very large scale integration co-design

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A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

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IEEE ACCESS 2017年 5卷 20965-20984页

作者： Hailes, Peter Xu, Lei Maunder, Robert G. Al-Hashimi, Bashir M. Hanzo, Lajos Univ Southampton Sch Elect & Comp Sci Southampton SO17 1BJ Hants England Intel Corp Programmable Solut Grp San Jose CA 95134 USA

Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasi-cyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance.

关键词： Digital communication error correction codes low-density parity check (LDPC) codes field-programmable gate array iterative decoding

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Development of a New High Speed Dual-Channel Impulse Ground Penetrating Radar

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IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2014年第3期7卷 753-760页

作者： Venkatachalam, Anbu Selvam Xu, Xianlei Huston, Dryver Xia, Tian Univ Vermont Sch Engn Burlington VT 05405 USA

This paper presents the development of a dual channel, air coupled Ultra-Wideband (UWB) Ground Penetrating Radar (GPR) targeting highway pavements and bridge deck inspections. Compared to most existing GPRs with a single channel and low survey speeds, our GPR possesses competitive features, including wide area coverage, high spatial resolution and operating capability at normal highway driving speed (up to 60 mph). The system has a two-channel microwave front end, a high speed (8 Gsps) real time data acquisition unit, a high throughput multi-thread data transmission and storage module, and a customized low-cost control element developed in a field-programmable gate array (FPGA). Experiments with different steel reinforcing bars establish GPR system performance.

关键词： field-programmable gate array ground penetrating radar ultra-wideband (UWB)

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FPGA-Embedded Anomaly Detection System for Milling Process

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IEEE ACCESS 2021年 9卷 124059-124069页

作者： Zabinski, Tomasz Hajduk, Zbigniew Kluska, Jacek Gniewek, Leslaw Rzeszow Univ Technol Dept Elect & Comp Engn PL-35959 Rzeszow Poland

The main goal of this work is to design a supervising controller able to detect an anomaly in the milling process and implement the soultion in field programmable gate array (FPGA) chip. Executing this task, the controller continuously monitors the vibration signal coming from the acceleration sensor, installed on the milling machine, and striving to isolate new vibration patterns which are different from typical patterns recorded for the correct milling process. The detection method relies on determining selected signal features in the frequency domain and applying an auto-associative neural network (AANN) for novelty detection. It has been shown that by exercising the frequency spectrum of the vibration signal, extracting specific features of the signal's spectrum, and using an auto-associative neural network, it is possible to detect anomalies in a milling process with relatively high efficiency. The accuracy, sensitivity, specificity, precision, and false alarm rate are equal to 94.3, 100, 91.2, 88.9, and 8.8 percent. All necessary calculations can be accomplished by the developed single-chip FPGA embedded supervising controller. The controller allows high-speed calculations under low power consumption. It characterizes high reliability and low price compared to typically encountered solutions.

关键词： Milling Anomaly detection field programmable gate arrays Tools Vibrations Feature extraction Real-time systems Anomaly detection autoencoder field-programmable gate array vibration analysis

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The architecture of a fault-tolerant modular neurocomputer based on modular number projections

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NEUROCOMPUTING 2018年 272卷 96-107页

作者： Chervyakov, N. I. Lyakhov, P. A. Babenko, M. G. Lavrinenko, I. N. Lavrinenko, A. V. Nazarov, A. S. North Caucasus Fed Univ Dept Appl Math & Math Modeling Stavropol Russia North Caucasus Fed Univ Dept Higher Algebra & Geometry Stavropol Russia

This paper suggests a rather efficient architecture for an error correction unit of a residue number system (RNS) that is based on a redundant RNS (RRNS) and applied in parallel data processing structures owing to its capability to improve information stability in calculations. However, the high efficiency of error correction is still not achieved due to the need in the expensive and complex operators that require substantial computational resources and considerable execution time. The suggested error correction method employs the Chinese remainder theorem (CRT) and artificial neural networks (ANN) that appreciably simplify the process of error detection, localization and correction. The key components of the error correction procedure are optimized using (a) the mixed radix conversion (MRC), i.e., the parallel conversion of the numbers from an RNS into the mixed radix number system (MRNS), and (b) the adaptation of neural networks to different sets of RNS moduli (bases) and also to the modular arithmetic during the computation of modular number projections and the restoration of the correct residue on a faulty module. Therefore, the expensive topological structures of neural networks are replaced with the reconfiguration using the weight coefficients switching. In comparison with the existing CRT-based method of projection calculation, the suggested method yields a 20%-30% reduction in power consumption, yet requiring by 10%-20% less FPGA resources for implementation. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Modular neurocomputer Residue number system Fault-tolerance Digital neuron Finite ring neural network field-programmable gate array

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GENERAL-PURPOSE SYSTOLIC arrayS

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COMPUTER 1993年第11期26卷 20-31页

作者： JOHNSON, KT HURSON, AR SHIRAZI, B Pennsylvania State Univ. University Park PA

Technology growth has produced computing environments that make it feasible to attack demanding scientific applications on a larger scale. Innovative applications like text recognition and image processing rely on computationally intensive operations requiring massive parallelism (for example, large-matrix multiplication, feature extraction, and cluster analysis). Systolic arrays are ideally suited for computationally intensive applications. Falling into an area between vector computers and massively parallel computers, systolic arrays typically combine intensive local communication and computation with decentralized parallelism in a compact package. This article chronicles the extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream) and MIMD (multiple-instruction stream, multiple-data stream) architectures, and, more recently, to hybrid architectures that combine both commercial and FPGA (field-programmable gate array) technologies. The authors present a taxonomy for systolic organizations (special purpose, programmable, reconfigurable, and hybrid), discuss each architecture's methods of exploiting concurrencies, and compare performance attributes of each. The authors also describe a number of implementation issues that determine a systolic array's performance efficiency (algorithms and mapping, system integration through memory subsystems, cell granularity, and extensibility to a wide variety of topologies, among others). The authors predict that, with technological advances, future systolic architectures will be based on reconfigurable FPGA architecture. They argue that general-purpose systolic arrays cannot be overlooked as a solution to the intensive computational performance requirements of tomorrow's applications.

关键词： MIMD SIMD cell granularity field-programmable gate array hybrid architectures logic arrays performance attributes system integration systolic array architecture systolic arrays taxonomy

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Evaluating FPGA-based denoising techniques for improved signal quality in electrocardiograms

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2024年第1期120卷 93-107页

作者： Keerthiga, G. Kumar, S. Praveen Saveetha Engn Coll Dept Elect & Commun Engn Chennai Tamilnadu India

The alarming mortality rates associated with cardiac abnormalities emphasize the critical need for early and accurate detection of heart disorders to mitigate severe health consequences for patients. Electrocardiograms (ECG) are commonly employed instruments for the examination of cardiac disorders, with a preference for noise-free ECG signals to ensure precise interpretation. However, ECG signal recordings are susceptible to environmental interferences, including patient movement and electrode positioning. This paper introduces a hardware implementation for denoising ECG signals, leveraging a novel method by integrating high-order Synchrosqueezing Transform, Detrended Fluctuation Analysis, and Non-Local-Mean filter optimized by Particle Swarm Optimization (HSST-DFA-PSO-NLM) techniques on field-programmable gate array (FPGA) platforms. FPGA-based processing units are chosen for their outstanding performance attributes, including high re-programmability, speed, architectural flexibility, and low power consumption, resulting in efficient signal processing. The effectiveness of the designed filtering algorithm is evaluated using key criteria, including Signal-to-Noise Ratio (SNR) and Root Mean Square Error (RMSE) for performance assessment. Additionally, resource utilization metrics such as Look-Up Tables (LUTs), Flip Flops, and DSP Blocks, as well as power consumption measures including dynamic power and static or leakage power, are analysed across various FPGA boards (Virtex and Zedboards) utilizing the VIVADO environment. Comparative analyses are conducted to identify the most suitable FPGA board for implementation, highlighting the superior performance of the proposed design. Remarkably, the proposed denoising solution gives excellent SNR of 29.56, 29.68, and 28.86 by denoising various ECG noises. The RMSE attained by the model is also less than 0.05. This research advances the field of cardiac disorder detection by providing a reliable and efficient FPGA-based sol

关键词： Electrocardiogram Signal-to-noise ratio Denoise field-programmable gate array Zedboard Power consumption

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Design and development of multi-channel front end electronics based on dual-polarity charge-to-digital converter for SiPM detector applications

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Nuclear Science and Techniques 2023年第2期34卷 1-12页

作者： Yu‑Ying Li Chang‑Yu Li Kun Hu Institute of Frontier and Interdisciplinary Science Shandong UniversityQingdao 266237China

With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and *** FEE consists of an analog board and FPGA *** analog board incorporates commercial amplifiers,resistors,and *** FPGA board is composed of a low-cost *** electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based *** PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array *** experimental results show that FEE can process dual-polarity charge signals from the SiPM *** addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 ***,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.

关键词： Readout electronics Charge measurement Radiation detector Silicon photomultiplier field-programmable gate array

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A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第11期71卷 4738-4742页

作者： Lee, Jaewon Jang, Seoyoung Braendli, Matthias Morf, Thomas Kossel, Marcel Francese, Pier-Andrea Kim, Gain Daegu Gyeongbuk Inst Sci & Technol Dept Elect Engn & Comp Sci Daegu 42988 South Korea IBM Res Europe Zurich Lab Dept Emerging Comp & Circuits CH-8803 Ruschlikon Switzerland

This brief presents a 2-lane discrete multitone (DMT) wireline receiver (RX) with a far-end crosstalk (FEXT) cancellation and its implementation on the ZCU111 RFSoC evaluation board for real-time functional verification. The RX datapath is implemented with the 64-parallel 128-tap multi-path delay-feedback (MDF) fast Fourier transform (FFT) to optimize resources and throughput. The multiple-input, multiple-output (MIMO) frequency-domain equalizer (FDE) compensates both channel insertion loss (IL) and FEXT based on coefficients computed from an on-chip pilot-assist channel estimation (CHEST). The platform includes a programmable logic (PL) for a DMT digital signal processor (DSP) running at 32 MHz, 2.048 GS/s data converters, and intersymbol interference (ISI)/FEXT board. This system enables the reflection of a realistic hardware impairment and real-time transceiver (TRX) operation with a quick bit error rate (BER) test. The measurement demonstrates that the MIMO DMT significantly improves a BER from 1.0E-2 to 5.8E-7 when the FEXT is canceled for a channel exhibiting 15 dB of IL and 10 dB of IL-to-crosstalk ratio (ICR) at Nyquist frequency.

关键词： MIMO communication Fast Fourier transforms Signal to noise ratio Symbols Real-time systems Loading field programmable gate arrays Serial link ADC-based serial link wireline transceiver discrete multitone DMT far-end crosstalk FEXT field-programmable gate array FPGA RFSoC

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Automatic cache partitioning method for high-level synthesis

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MICROPROCESSORS AND MICROSYSTEMS 2019年 67卷 71-81页

作者： Jones, Bryant Hanna, Darrin M. Oakland Univ Dept Elect & Comp Engn Rochester MI 48309 USA

Existing algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS), allowing for quick prototyping or deployment of embedded designs. High-level software is written with a single main memory in mind, whereas hardware designs can take advantage of many parallel memories. The translation and optimization of memory usage, and the generation of resulting architectures, is important for high-performance designs. Tools provide optimizations on memory structures targeting data reuse and partitioning, but generally these are applied separately for a given object in memory. Memory access that cannot be effectively optimized is serialized to the memory, hindering any further parallelization of the surrounding generated hardware. In this work, we present an automated optimization method for creating custom cache memory architectures for HLS generated designs. Our optimization uses runtime profiling data, and is performed at a localized scope. This method combines data reuse savings and memory partitioning to further increase the potential parallelism and alleviate the serialized memory access, increasing performance. Comparisons are made against architectures without this optimization, and against other HLS caching approaches. Results are presented showing this method requires 72% of the number of execution cycles compared to a single-cache design, and 31% compared to designs with no caches. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Compilers field-programmable gate array High-level synthesis Caches Memory architectures

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