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Evaluating FPGA-based denoising techniques for improved signal quality in electrocardiograms

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2024年第1期120卷 93-107页

作者： Keerthiga, G. Kumar, S. Praveen Saveetha Engn Coll Dept Elect & Commun Engn Chennai Tamilnadu India

The alarming mortality rates associated with cardiac abnormalities emphasize the critical need for early and accurate detection of heart disorders to mitigate severe health consequences for patients. Electrocardiograms (ECG) are commonly employed instruments for the examination of cardiac disorders, with a preference for noise-free ECG signals to ensure precise interpretation. However, ECG signal recordings are susceptible to environmental interferences, including patient movement and electrode positioning. This paper introduces a hardware implementation for denoising ECG signals, leveraging a novel method by integrating high-order Synchrosqueezing Transform, Detrended Fluctuation Analysis, and Non-Local-Mean filter optimized by Particle Swarm Optimization (HSST-DFA-PSO-NLM) techniques on field-programmable gate array (FPGA) platforms. FPGA-based processing units are chosen for their outstanding performance attributes, including high re-programmability, speed, architectural flexibility, and low power consumption, resulting in efficient signal processing. The effectiveness of the designed filtering algorithm is evaluated using key criteria, including Signal-to-Noise Ratio (SNR) and Root Mean Square Error (RMSE) for performance assessment. Additionally, resource utilization metrics such as Look-Up Tables (LUTs), Flip Flops, and DSP Blocks, as well as power consumption measures including dynamic power and static or leakage power, are analysed across various FPGA boards (Virtex and Zedboards) utilizing the VIVADO environment. Comparative analyses are conducted to identify the most suitable FPGA board for implementation, highlighting the superior performance of the proposed design. Remarkably, the proposed denoising solution gives excellent SNR of 29.56, 29.68, and 28.86 by denoising various ECG noises. The RMSE attained by the model is also less than 0.05. This research advances the field of cardiac disorder detection by providing a reliable and efficient FPGA-based sol

关键词： Electrocardiogram Signal-to-noise ratio Denoise field-programmable gate array Zedboard Power consumption

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FPGA-Based Hierarchical Configuration Method for Conservation-Oriented Ecological Garden Landscape for a Smart City Development

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JOURNAL OF TESTING AND EVALUATION 2023年第3期51卷 1555-1570页

作者： Yu, Jia Yang, Rui Shenyang Univ Coll Life Sci & Bioengn Shenyang 110044 Peoples R China Shenyang Vanke Real Estate Dev Co Ltd Design Dept Shenyang 110044 Peoples R China

More and more attention is paid to development and conservation at home. In response to national policies, this paper proposes a field-programmable gate array (FPGA)-based hierar-chical configuration method for conservation-oriented ecological garden landscape to build sustainable ecological garden landscapes. Following the principles of uniformity, adapting measures to local conditions, and aesthetics in hierarchical configuration of conservation -oriented ecological garden landscape, this paper gives comprehensive consideration to exami-nation factors and landscape plant rationality in hierarchical configuration and takes scenic beauty estimates to evaluate the plant landscape configuration effect. Under the guidance of hierarchical configuration principles and evaluation indicators for conservation-oriented ecological garden landscape, this paper adopts the FPGA partition algorithm to design the hierarchical conservation design model of the garden landscape. In the subsequent hierarchical configuration of ecological garden landscape, the lowest energy consumption is maintained, plant communities are reasonably collocated to achieve hierarchical configuration of the gar-den landscape, and energy consumption in the landscape is reduced through measures such as material and water conservation, thus achieving hierarchical configuration of conservation -oriented ecological garden landscape. Experimental research results of a forest park in Quanzhou conclude that this method can achieve hierarchical configuration of the ecological garden landscape in the forest park. Plant collocation is reasonable in the more aesthetic and concise landscape configuration. At the same time, the configuration process saves water re-sources and reduces energy consumption, demonstrating the advantage of low configuration costs.

关键词： field-programmable gate array conservation-oriented ecology garden landscape hierarchical configuration

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Automatic cache partitioning method for high-level synthesis

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MICROPROCESSORS AND MICROSYSTEMS 2019年 67卷 71-81页

作者： Jones, Bryant Hanna, Darrin M. Oakland Univ Dept Elect & Comp Engn Rochester MI 48309 USA

Existing algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS), allowing for quick prototyping or deployment of embedded designs. High-level software is written with a single main memory in mind, whereas hardware designs can take advantage of many parallel memories. The translation and optimization of memory usage, and the generation of resulting architectures, is important for high-performance designs. Tools provide optimizations on memory structures targeting data reuse and partitioning, but generally these are applied separately for a given object in memory. Memory access that cannot be effectively optimized is serialized to the memory, hindering any further parallelization of the surrounding generated hardware. In this work, we present an automated optimization method for creating custom cache memory architectures for HLS generated designs. Our optimization uses runtime profiling data, and is performed at a localized scope. This method combines data reuse savings and memory partitioning to further increase the potential parallelism and alleviate the serialized memory access, increasing performance. Comparisons are made against architectures without this optimization, and against other HLS caching approaches. Results are presented showing this method requires 72% of the number of execution cycles compared to a single-cache design, and 31% compared to designs with no caches. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Compilers field-programmable gate array High-level synthesis Caches Memory architectures

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High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2^m)

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IET INFORMATION SECURITY 2017年第2期11卷 66-77页

作者： Rashidi, Bahram Farashahi, Reza Rezaeian Sayedi, Sayed Masoud Isfahan Univ Technol Dept Elect & Comp Engn Esfahan *** Iran Isfahan Univ Technol Dept Math Sci Esfahan *** Iran Inst Res Fundamental Sci IPM Sch Math POB 19395-5746 Tehran Iran

In this study high-performance and high-speed field-programmable gate array (FPGA) implementations of polynomial basis Itoh-Tsujii inversion algorithm (ITA) over GF(2(m)) constructed by irreducible trinomials and pentanomials are presented. The proposed structures are designed by one field multiplier and k-times squarer blocks or exponentiation by 2(k), where k is a small positive integer. The k-times squarer blocks have an efficient tree structure with low critical path delay, and the multiplier is based on a proposed high-speed digit-serial architecture with minimum hardware resources. Furthermore, to reduce the computation time of ITA, the critical path of the circuit is broken to finer path using several registers. The computation times of the structure on Virtex-4 FPGA family are 0.262, 0.192 and 0.271 mu s for GF(2(163)), GF(2(193)) and GF(2(233)), respectively. The comparison results with other implementations of the polynomial basis Itoh-Tsujii inversion algorithm verify the improvement in the proposed architecture in terms of speed and performance.

关键词： field programmable gate arrays polynomials multiplying circuits flip-flops trees (mathematics) logic design Virtex-4 FPGA family registers hardware resources digit-serial architecture path delay tree structure k-times squarer blocks field multiplier pentanomials irreducible trinomials field-programmable gate array ITA polynomial basis Itoh-Tsujii inversion algorithm

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New wind turbine emulator based on DC machine: hardware implementation using FPGA board for an open-loop operation

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IET CIRCUITS DEVICES & SYSTEMS 2019年第6期13卷 896-902页

作者： Moussa, Intissar Bouallegue, Adel Khedher, Adel Univ Sousse Elect Engn Ecole Natl Ingenieurs Sousse LATIS Lab Adv Technol & Intelligent Syst Sousse 4023 Tunisia

This work deals with the development of an open-loop wind turbine emulator to verify the system operation with respect to the wind profile. The emulator consists essentially of a 300 W DC motor powered by DC/DC buck converter which controlled through field-programmable gate array (FPGA) and pulse-width modulation strategy. The motor rotational speed allows to imitate proportionally different wind velocity. A hardware test bench based on the fast prototyping method using MATLAB/Xilinx System Generation (XSG) environment and FPGA board of wind turbine simulator is built to validate the simulation results. Simulation and experimental results confirm the efficiency of the implemented method to make the proposed emulator able to react as a real wind in laboratory.

关键词： DC-DC power convertors machine control wind turbines DC motors field programmable gate arrays DC machine hardware implementation FPGA board open-loop operation open-loop wind turbine emulator system operation wind profile 300 W DC motor field-programmable gate array pulse-width modulation strategy motor rotational speed proportionally different wind velocity hardware test bench wind turbine simulator power 300 0 W implemented method

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Pseudo-Sensorless High-Performance Bilateral Teleoperation by Sliding-Mode Control and FPGA

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IEEE-ASME TRANSACTIONS ON MECHATRONICS 2014年第1期19卷 384-393页

作者： Hace, Ales Franc, Marko Univ Maribor Inst Robot SLO-2000 Maribor Slovenia Isomat Doo Mezica 2392 Slovenia

This paper proposes a pseudo-sensorless implementation of scaled bilateral teleoperation. It is based on Hall effect sensors that are built within the motor housing. The proposed implementation requires no external sensor that can deteriorate system dynamics and performance. The integrated sensors have been used both for position measurement and external force estimation that are necessary in high-performance bilateral teleoperation. Nevertheless, system perturbation dynamics may always appear in a practical mechatronic system. Therefore, the chattering-free sliding-mode control algorithm is applied that ensures robustness toward the disturbances, and yet is easy to implement. The data acquisition algorithms as well as the control algorithm are implemented by field-programmable gate array (FPGA) in order to provide high control rate that can further increase robustness required for haptic fidelity of the system for scaled teleoperation. The applied algorithms along with the FGPA implementation were validated by the 2-DoF experimental system. It has been shown that the proposed pseudo-sensorless implementation by FPGA provides high bilateral teleoperation performance.

关键词： Bilateral teleoperation field-programmable gate array haptics sliding-mode control (SMC)

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Algorithms for an FPGA switch module routing problem with application to global routing

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1997年第1期16卷 32-46页

作者： Thakur, S Chang, YW Wong, DF Muthukrishnan, S NATL CHIAO TUNG UNIV DEPT COMP & INFORMAT SCI HSINCHU 300 TAIWAN UNIV TEXAS DEPT COMP SCI AUSTIN TX 78712 USA LUCENT TECHNOL MURRAY HILL NJ 07974 USA

We consider a switch module routing problem for symmetrical-array field-programmable gate arrays (FPGA's). This problem was first introduced in [21], They used it to evaluate the routability properties of switch modules which they proposed, Only an approximation algorithm for the problem was proposed by them, We give an optimal algorithm for the problem based on integer linear programming (ILP), Experiments show that this formulation leads to fast and efficient solutions to practical-sized problems, We then propose a precomputation that eliminates the need to use ILP era-line, We also identify special cases of this problem that reduce to problems for whom efficient algorithms are known, Thus, the switch module routing problem can be solved in polynomial time for these special cases, Using our solution to the switch module routing problem, we propose a new metric to estimate the congestion in each switch module in the FPGA. We demonstrate the use of this metric in a global router, A comparison with a global router guided by the density of the routing channels shows that our metric leads to far superior global and detailed routing solutions.

关键词： field-programmable gate array global routing

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VLSI implementation of reversible logic gates cryptography with LFSR key

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MICROPROCESSORS AND MICROSYSTEMS 2019年 69卷 68-78页

作者： Karunamurthi, Saranya Natarajan, Vijeyakumar Krishnasamy Dr Mahalingam Coll Engn & Technol Dept Elect & Elect Engn Coimbatore Tamil Nadu India Dr Mahalingam Coll Engn & Technol Dept Elect & Commun Engn Coimbatore Tamil Nadu India

The reversible computation is an emerging research field, which is used in different applications such as optical computing, digital signal processing, nanotechnologies, bio-information and in low-power computation. In present days, these applications require security algorithm to keep the information securely. The power and area analysis are one of the major challenges to mathematically secure cryptography protocols. Moreover, hackers can take confidential data while it passes through the transmission line. To overcome this problem, Reversible logic cryptography design (RLCD) architecture is introduced in this paper. With the help of RLCD, the encryption and decryption architecture is designed. Linear feedback shift register (LFSR) is required to produce a key which is given to the encryption and decryption block. The application specified integrated chip (ASIC) and field-programmable gate array (FPGA) performances are evaluated for both existing and proposed method. More than 7% of the ASIC performances improved in RLCD-LFSR method compared to the conventional methods. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Application specified integrated chip field-programmable gate array Linear feedback shift register Power Reversible logic cryptography design

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Design of a Multiple Pseudorandom Number Generator Combined Chaotic System With RNS and Its Application to Secure Image Processing

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IEEE ACCESS 2024年 12卷 155246-155258页

作者： Liu, Chien-Chun Chen, Chih-Chiang Yan, Jun-Juh Liao, Teh-Lu Natl Cheng Kung Univ Dept Engn Sci Tainan 70101 Taiwan Air Force Inst Technol Dept Aircraft Engn Kaohsiung 82063 Taiwan Natl Cheng Kung Univ Dept Syst & Naval Mechatron Engn Tainan 70101 Taiwan Natl Chin Yi Univ Technol Dept Elect Engn Taichung 41107 Taiwan

This paper presents a novel approach to designing a multiple pseudorandom number generator (MPNG) through the integration of several key techniques. Specifically, the method leverages the chaotic dynamics of the 2D Tinkerbell system, a residue number system (RNS), and XOR operations to generate multiple sets of pseudorandom number sequences. The MPNG offers several advantages, including a simple design and low hardware resource requirements. Implemented using a field-programmable gate array (FPGA), it applies each chaotic system state to produce three sets of random number sequences, achieving a generation rate three times higher. The generated sequences are rigorously evaluated using the NIST SP800-22 and Diehard test suites, along with Shannon entropy and histogram analyses, all of which confirm their randomness. The results pass all NIST SP800-22 and Diehard test items, demonstrating the properties of random numbers. Additionally, this paper proposes a synchronization controller to achieve state synchronization between the master system and the slave system, enabling symmetric encryption and decryption applications for secure image processing.

关键词： Chaotic communication Encryption Main-secondary Generators Synchronization field programmable gate arrays NIST Hardware Noise measurement Receivers Multiple pseudorandom number generator chaotic system residue number system field-programmable gate array

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High-speed target tracking algorithm for the pulse-sequence-based image sensor

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IET IMAGE PROCESSING 2021年第5期15卷 1157-1165页

作者： Xu, Jiangtao Wang, Xiangfeng Gao, Zhiyuan Nie, Kaiming Tianjin Univ Sch Microelect Tianjin Peoples R China Tianjin Key Lab Imaging & Sensing Microelect Tech Tianjin Peoples R China

This paper proposed a high-speed target tracking algorithm based on the pulse-sequence-based image sensor. The algorithm separates the target from the background through the statistical distribution of the pulses in a single frame of data. In order to achieve more accurate target tracking, the phenomenon of image lag in the process of capturing the high-speed moving target is studied. The positioning deviation is compensated by estimating the image lag length of the moving target. The algorithm is implemented with pipeline processing on field-programmable gate array (FPGA). The positioning accuracy of the algorithm is verified with input data from a pulse-sequence image sensor model. The verification results show that the maximum position deviation of the target at different speeds is 0.94 pixels. In the experiment of tracking a 40 m/s moving ball, this algorithm can provide real-time position information within 44 ns.

关键词： time 44.0 ns high-speed moving target velocity 40.0 m/s high-speed target tracking algorithm pulse-sequence image sensor model field programmable gate arrays FPGA target tracking image lag length Logic circuits statistical distribution Logic and switching circuits Digital signal processing field-programmable gate array accurate target tracking image sensors Image sensors speed target tracking algorithm Signal processing and detection

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