检索结果-内蒙古大学图书馆

A Tag Based Random Order Vector Reduction Circuit

IEEE ACCESS 2020年 8卷 41502-41515页

作者： Huang, Yihua Huang, Wenjin Chen, Rui Wu, Huangtao Wei, Ming Sun Yat Sen Univ Sch Elect & Informat Technol Guangzhou 510006 Peoples R China

Vector reduction is a very common operation to reduce a vector into a single scalar value in many scientific and engineering application scenarios. Therefore a fast and efficient vector reduction circuit has great significance to the real-time system applications. Usually the pipeline structure is widely adopted to increase the throughput of the vector reduction circuit and achieve maximum efficiency. In this paper, to deal with multiple vectors of variable length in random input sequence, a novel tag based fully pipelined vector reduction circuit is firstly proposed, in which a cache state module is used to queer and update the cache state of each vector. However, when the quantity of the input vector becomes large, a larger cache state module is required, which consumes more combinational logic and lower the operating frequency. To solve this problem, a high speed circuit is proposed in which the input vectors will be divided into several groups and sent into the dedicated cache state circuits, which can improve the operating frequency. Compared with other existing work, the prototype circuit and the improved circuit based on the prototype circuit can achieve the smallest Slices xus (<80% of the state-of-the-art work) for different input vector lengths. Moreover, both circuits can provide simple and efficient interface whose access timing is similar to that of a RAM. Therefore the circuits can be applied in a greater range.

关键词： Pipelines Hardware Clocks Adders field programmable gate arrays Binary trees Out of order field-programmable gate arrays fully pipelined vector reduction

来源：评论

学校读者我要写书评

暂无评论

A Reconfigurable Full-Digital Architecture for Angle of Arrival Estimation

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第3期71卷 1443-1455页

作者： Florio, Antonello Avitabile, Gianfranco Talarico, Claudio Coviello, Giuseppe Polytech Univ Bari Dept Elect & Informat Engn I-70125 Bari Italy Gonzaga Univ Dept Elect & Comp Engn Spokane WA 99258 USA

In recent years, Real-Time Localization Systems (RTLS) are gaining significant attention from the scientific community. Usually, RLTS rely on positioning techniques based on the electromagnetic (e.m.) propagation properties of the received signals. Among the many possible approaches, RTLS based on the Angle-of-Arrival (AoA) estimation allows for accurate results with a comparatively lower number of receivers. In this work, we propose a novel, fully digital synchronous architecture for AoA estimation based on phase interferometry. After reviewing the state-of-the-art on full-hardware techniques for localization, the main blocks composing the proposed architecture, are discussed in detail, along with their dimensioning equations. The granularity with which the system estimates the phase shifts used to compute the AoA is reconfigurable according to the desired accuracy. The architecture is lightweight and computes the AoA in real-time. To validate the proposed approach, the RTLS architecture has been implemented on an Intel Cyclone IV E EP4CE115F29C7 FPGA board interfaced with a custom-designed receiver front-end, and experimental results on benchmark applications have been collected and analyzed.

关键词： Direction-of-arrival angle-of-arrival localization field-programmable gate arrays phase detection phase interferometry real-time localization systems

来源：评论

学校读者我要写书评

暂无评论

FYalSAT: High-Throughput Stochastic Local Search K-SAT Solver on FPGA

引用

IEEE ACCESS 2024年 12卷 65503-65512页

作者： Choi, Young-Kyu Kim, Changsoo Inha Univ Dept Comp Engn Incheon 22212 South Korea Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

The satisfiability (SAT) problem is a fundamental challenge in computing and has a broad range of applications. This problem is NP-complete, and many algorithmic and architectural improvements have aimed at accelerating the SAT solver. But most existing stochastic local search (SLS) hardware solvers still rely on the outdated WalkSAT algorithm, and they have a reduced performance when handling problems with a large number of literals per clause. In this paper, we present FYalSAT, a field-programmable gate array (FPGA) based SLS SAT solver designed for high throughput. We incorporate a conflict-free data rearrangement scheme and a novel synchronization method to increase the parallelism. We also apply various optimizations such as clause prefetching, module overlapping, and pipelining to improve the performance. Experimental results demonstrate that FYalSAT outperforms the throughput of existing SLS FPGA solvers by 9.07 x - 110 x for benchmarks with a large number of literals per clause.

关键词： field-programmable gate arrays satisfiability problem stochastic local search accelerator architecture

来源：评论

学校读者我要写书评

暂无评论

Design considerations for soft embedded programmable logic cores

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2005年第2期40卷 485-497页

作者： Wilton, SJE Kafafi, N Wu, JCH Bozman, KA Aken'Ova, VO Saleh, R Univ British Columbia Dept Elect & Comp Engn Vancouver BC V6T 1Z4 Canada PMC Sierra Burnaby BC V5A 4V7 Canada Altera Toronto ON M5S 1S4 Canada

As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" rectangular layouts. In this paper, we focus on an alternative approach for fine-grain programmability: vendors supply a synthesizable RTL version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers in terms of speed, density and power overhead, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC or SoC. When the required amount of programmable logic is small, this ease of use may be more important than the increased overhead. This paper presents two synthesizable "soft" programmable logic core architectures and describes their associated place and route issues. We compare the two architectures. to each other, and to a "hard" programmable logic core. We also show how these cores can be made more efficient by creating a nonrectangular architecture, an option not usually. available to "hard" core vendors. Finally, a proof-of-concept integrated circuit containing one of these cores is described.

关键词： field-programmable gate arrays programmable logic SoC design

来源：评论

学校读者我要写书评

暂无评论

An efficient systolic array grid-based structure of the robust Bayesian regularization technique for real-time enhanced imaging in uncertain remote sensing environment

引用

JOURNAL OF REAL-TIME IMAGE PROCESSING 2017年第4期13卷 783-796页

作者： Castillo Atoche, A. Carrasco Alvarez, R. Palma Marrufo, O. Vazquez Castillo, J. Univ Autonoma Yucatan Dept Mechatron Ave Ind Contaminantes S-N Perifer Norte Merida Yucatan Mexico Univ Guadalajara Elect Engn Div Blvd Marcelino Garcia Barragan 1421 Guadalajara Jalisco Mexico Univ Quintana Roo Div Sci Blvd Bahia S-N Esq Ignacio Comonfort Chetmal Quintana Roo Mexico

In this paper, we address a hardware implementation of the efficient robust Bayesian regularization architecture for the real-time enhancement of large-scale remote sensing (RS) imaging. The efficient sense of the proposed architecture is related to the high-performance embedded implementation that is achieved with the aggregation of parallel computing and systolic array design techniques in a novel grid connected-based accelerator. Then, the developed high-speed accelerator is integrated with an embedded processor via the HW/SW co-design paradigm. The presented approach is used for solving RS image enhancement/reconstruction of the ill-conditioned inverse spatial spectrum pattern estimation problems via an interesting low-cost high-performance embedded computing solution. Finally, we show the achieved results and how we drastically reduced the computational load for real-world large-scale geospatial images.

关键词： Remote sensing Real-time systems Systolic array architectures field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

MATRIX STRUCTURES AND PARALLEL ALGORITHMS FOR IMAGE SUPERRESOLUTION RECONSTRUCTION

引用

SIAM JOURNAL ON MATRIX ANALYSIS AND APPLICATIONS 2010年第4期31卷 1873-1893页

作者： Zhang, Qiang Guy, Richard T. Plemmons, Robert J. Wake Forest Univ Hlth Sci Dept Biostat Sci Winston Salem NC 27159 USA Wake Forest Univ Dept Math Winston Salem NC 27109 USA Wake Forest Univ Dept Math & Comp Sci Winston Salem NC 27109 USA

Computational resolution enhancement (superresolution) is generally regarded as a memory-intensive process due to the large matrix-vector calculations involved. In this paper, a detailed study of the structure of the n(2) x n(2) superresolution matrix is used to decompose the matrix into nine matrices of size l(2) x l(2), where l is the upsampling factor. As a result, previously large matrix-vector products can be broken into many small, parallelizable products. An algorithm is presented that utilizes the structural results to perform superresolution on compact, highly parallel architectures such as field-programmable gate arrays.

关键词： image superresolution field-programmable gate arrays parallel computation structured matrices

来源：评论

学校读者我要写书评

暂无评论

Adapting FreeRTOS for multicores: an experience report

引用

SOFTWARE-PRACTICE & EXPERIENCE 2014年第9期44卷 1129-1154页

作者： Mistry, James Naylor, Matthew Woodcock, Jim British Telecommun PLC Ipswich IP5 3RE Suffolk England Univ York Dept Comp Sci York YO10 5GH N Yorkshire England

Multicore processors are ubiquitous. Their use in embedded systems is growing rapidly, and given the constraints on uniprocessor clock speeds, their importance in meeting the demands of increasingly processor-intensive embedded applications cannot be understated. To harness this potential, system designers need to have available to them embedded operating systems with built-in multicore support for widely available embedded hardware. This paper documents our experience of adapting FreeRTOS, a popular embedded real-time operating system, to support multiple processors. A working multicore version of FreeRTOS that is able to schedule tasks on multiple processors as well as provide full mutual-exclusion support for use in concurrent applications is presented. Mutual exclusion is achieved in an almost completely platform-agnostic manner, preserving one of FreeRTOS's most attractive features: portability. Copyright (c) 2013 John Wiley & Sons, Ltd.

关键词： embedded systems operating systems multicore computing task scheduling software-based mutual exclusion field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Exploring the design-space for FPGA-based implementation of RSA

引用

MICROPROCESSORS AND MICROSYSTEMS 2004年第4期28卷 183-191页

作者： Cilardo, A Mazzeo, A Romano, L Saggese, GP Univ Naples Federico II I-80125 Naples Italy

In this paper, we present two alternative architectures for implementing the Rivest-Shamir-Adleman (RSA) algorithm on reconfigurable hardware. Both architectures are innovative, especially with respect to the implementation of modular multiplication. As to the area vs time trade-off, the two solutions are at the extremes of the design-space, since one adopts a word serial approach, while the other has a fully parallel organization. Based on the analysis of these architectures for different values of the serialization factor, we explore the design-space for the field-programmable gate array (FPGA)-based implementation of the RSA algorithm. We systematically analyze and compare the results of the two design processes with respect to two fundamental metrics, namely execution time and FPGA resource usage. We emphasize pros and cons and comment trade-offs of the two design alternatives. (C) 2004 Elsevier B.V. All rights reserved.

关键词： field-programmable gate arrays Rivest-Shamir-Adleman cryptosystem Montgomery multiplication reconfigurable computing

来源：评论

学校读者我要写书评

暂无评论

High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines

引用

IEEE TRANSACTIONS ON NEURAL NETWORKS 2010年第11期21卷 1780-1792页

作者： Le Ly, Daniel Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 x 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

关键词： Boltzmann machines computer architecture field-programmable gate arrays neural network hardware parallel processing

来源：评论

学校读者我要写书评

暂无评论

Damping of Subsynchronous Control Interactions in Large-Scale PV Installations Through Faster-Than-Real-Time Dynamic Emulation

引用

IEEE ACCESS 2021年 9卷 128481-128493页

作者： Cao, Shiqi Lin, Ning Dinavahi, Venkata Univ Alberta Elect & Comp Engn Dept Edmonton AB T6G 2R3 Canada Powertech Labs Inc Surrey BC V3W 7R7 Canada

Large-scale photovoltaic (PV) power plant has witnessed a dramatic increase in the integration into transmission and distribution network, manifesting subsynchronous control interaction (SSCI) when the host grid is weak. In this work, the oscillation modes of a typical PV network are analyzed, and a faster-than-real-time (FTRT) emulation is proposed for predicting the SSCI and consequently mitigating its impacts on AC grid by taking the effective active/reactive power control action. The electromagnetic transient (EMT) simulation is utilized to model the PV panels and converter stations to reflect the actual dynamic process. Meanwhile, the AC grid undergoes transient stability (TS) simulation to obtain a high speed up over real-time, and consequently, a power-voltage interface is adopted for the coexistence of different simulation methods. The reconfigurability and parallelism of the field-programmable gate arrays (FPGAs) enable the EMT-TS co-emulation strategy to run concurrently. With a remarkable 122 FTRT ratio, the proposed hardware emulation can provide an effective solution before the SSCI causes serious disruption following its detection. The hardware emulation results are validated by the off-line simulation tool Matlab/Simulink(R) and TSAT(R) in the DSATools((TM)) suite.

关键词： Emulation Power system stability Inverters Damping Voltage control Oscillators Hardware AC DC grid dynamic simulation electromagnetic transient faster-than-real-time field-programmable gate arrays hardware emulation parallel processing predictive control PV generation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：