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A Reconfigurable Full-Digital Architecture for Angle of Arrival Estimation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第3期71卷 1443-1455页

作者： Florio, Antonello Avitabile, Gianfranco Talarico, Claudio Coviello, Giuseppe Polytech Univ Bari Dept Elect & Informat Engn I-70125 Bari Italy Gonzaga Univ Dept Elect & Comp Engn Spokane WA 99258 USA

In recent years, Real-Time Localization Systems (RTLS) are gaining significant attention from the scientific community. Usually, RLTS rely on positioning techniques based on the electromagnetic (e.m.) propagation properties of the received signals. Among the many possible approaches, RTLS based on the Angle-of-Arrival (AoA) estimation allows for accurate results with a comparatively lower number of receivers. In this work, we propose a novel, fully digital synchronous architecture for AoA estimation based on phase interferometry. After reviewing the state-of-the-art on full-hardware techniques for localization, the main blocks composing the proposed architecture, are discussed in detail, along with their dimensioning equations. The granularity with which the system estimates the phase shifts used to compute the AoA is reconfigurable according to the desired accuracy. The architecture is lightweight and computes the AoA in real-time. To validate the proposed approach, the RTLS architecture has been implemented on an Intel Cyclone IV E EP4CE115F29C7 FPGA board interfaced with a custom-designed receiver front-end, and experimental results on benchmark applications have been collected and analyzed.

关键词： Direction-of-arrival angle-of-arrival localization field-programmable gate arrays phase detection phase interferometry real-time localization systems

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FYalSAT: High-Throughput Stochastic Local Search K-SAT Solver on FPGA

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IEEE ACCESS 2024年 12卷 65503-65512页

作者： Choi, Young-Kyu Kim, Changsoo Inha Univ Dept Comp Engn Incheon 22212 South Korea Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

The satisfiability (SAT) problem is a fundamental challenge in computing and has a broad range of applications. This problem is NP-complete, and many algorithmic and architectural improvements have aimed at accelerating the SAT solver. But most existing stochastic local search (SLS) hardware solvers still rely on the outdated WalkSAT algorithm, and they have a reduced performance when handling problems with a large number of literals per clause. In this paper, we present FYalSAT, a field-programmable gate array (FPGA) based SLS SAT solver designed for high throughput. We incorporate a conflict-free data rearrangement scheme and a novel synchronization method to increase the parallelism. We also apply various optimizations such as clause prefetching, module overlapping, and pipelining to improve the performance. Experimental results demonstrate that FYalSAT outperforms the throughput of existing SLS FPGA solvers by 9.07 x - 110 x for benchmarks with a large number of literals per clause.

关键词： field-programmable gate arrays satisfiability problem stochastic local search accelerator architecture

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The Prism Bridge: Maximizing Inter-Chip AXI Throughput in the High-Speed Serial Era

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IEEE ACCESS 2023年 11卷 50867-50883页

作者： Drehmel, Robert Heiss, Hans-Ulrich Tech Univ Berlin Inst Telecommun Syst Fac Elect Engn & Comp Sci 4 D-10623 Berlin Germany

In this paper, we present the Prism Bridge, a soft IP core developed to bridge FPGA-MPSoC systems using high-speed serial links. Considering the current trend of ubiquitous serial transceivers with staggeringly increasing line rates, minimizing overhead and maximizing data throughput becomes paramount. Hence, our main design goal is to maximize bandwidth utilization for AXI data, which we realize through an advanced packetization mechanism. We give an overview of the Prism Bridge's design and analyze its half-duplex bandwidth utilization. Additionally, we discuss the results of the experiments we conducted to assess its real-world performance, including measurements of throughput and latency of various combinations of line rates, link-layer cores, and bridge cores. Using a serial link with a 16.375 Gbit/s line rate, the Prism Bridge with an advanced packetizing mechanism achieved an AXI write throughput of 1368.81 MiB/s and an AXI read throughput of 1376.61 MiB/s, an increase of 46.19% and 45.85%, respectively, compared with the de-facto industry-standard core. The advanced packetization mechanism had negligible impact on latency but required 69.14%-73.91% more LUTs and 33.62%-36.19% more flip-flops. We conclude that for most designs that support inter-chip AXI transactions and will not be limited to short transaction lengths, the higher data throughput of the Prism Bridge with an advanced packetization mechanism is worth its cost in additional logic resource utilization.

关键词： Clustering methods Magnetosphere Ion radiation effects Throughput Protocols Bandwidth field programmable gate arrays Computer architecture Cluster computing computer architecture field-programmable gate arrays high-speed serial inter-chip axi communication protocols

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High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 417-420页

作者： Nagar, Mitul Sudhirkumar Mathuriya, Aditya Patel, Sohan H. Engineer, Pinalkumar J. Sardar Vallabhbhai Natl Inst Technol Dept Elect Engn Surat 395007 India

Among various platforms for computer vision algorithms, FPGA has gained popularity as a low-power solution. These algorithms involve convolution operation which are extensively performed using signed multipliers. Hence, this work proposes high-speed and energy-efficient signed fixed-point multipliers for digital signal processing (DSP) applications. This work focuses on reducing the combinational path delay (CPD) using LUT-based Booth radix-4 partial product (PP) generation with Bewick's sign extension and Dadda-based concurrent PP reduction with carry save adder (CSA) for Xilinx (now AMD) FPGA. The proposed design eliminates the requirement of a long carry chain for PP reduction. The proposed multiplier reduces CPD by 3%, 4%, and 16% compared to the state-of-the-art (SoA) multiplier for 8x8 , 16x16 , and 32x32 sizes, respectively. We have also analyzed our proposed 32x32 multiplier by pipelining, which offers CPD and EDP reduction by 12.28% and 19.47% at the cost of a 3% and 80% increase in LUTs and flip-flops, respectively, compared to the combinatorial multiplier.

关键词： Table lookup field programmable gate arrays Adders Vegetation Standards Signal processing algorithms Resource management Booth radix-4 digital signal processing (DSP) energy-efficient field-programmable gate arrays signed fixedpoint multiplier

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Commissioning and Operation of the Upgraded Belle II DAQ System With PCI-Express-Based High-Speed Readout

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2023年第6期70卷 890-897页

作者： Lai, Y. -T. Bessner, M. Biswas, D. Charlet, D. Lau, T. S. Levit, D. Hartbrich, O. Higuchi, T. Itoh, R. Jules, E. Kapusta, P. Kunigo, T. Nakao, M. Nishimura, K. Park, S. Plaige, E. Purwar, H. Robbe, P. Sugiura, R. Suzuki, S. Y. Taurigna, M. Varner, G. Yamada, S. Zhou, Q. -D. Univ Tokyo Kavli Inst Phys & Math Universe IPMU Chiba 2778583 Japan Univ Hawaii Manoa Dept Phys & Astron Honolulu HI 96822 USA Univ Louisville Dept Phys & Astron Louisville KY 40292 USA Lab Phys Deux Infinis Irene Joliot Curie IJCLab F-91898 Orsay France Univ Paris Saclay Lab Phys Deux Infinis Irene Joliot Curie IJCLab CNRS IN2P3 F-91898 Orsay France High Energy Accelerator Res Org KEK Ibaraki 3050801 Japan Polish Acad Sci PAN Henryk Niewodniczanski Inst Nucl Phys IFJ PL-31342 Krakow Poland Univ Tokyo Fac Sci Dept Phys Tokyo 1130033 Japan Univ Tokyo Grad Sch Sci Tokyo 1130033 Japan Nagoya Univ Inst Adv Res Nagoya Aichi 4648601 Japan Nagoya Univ Kobayashi Maskawa Inst Nagoya Aichi 4648601 Japan

The Belle II experiment and the SuperKEKB collider are designed to operate under a higher luminosity compared to that of Belle for the improvement of rare $B$ meson decay study and new physics search. To break the bottleneck of bandwidth and to improve the stability in the operation of the Belle II data acquisition (DAQ) system, a new PCI-express-based readout system has been developed. The new system includes a PCI-express-based high-speed readout board (PCIe40), which was originally developed for the upgrades of the LHCb and ALICE experiments, the PCIe40 firmware, the slow control, and readout software running on a readout PC. The new readout system's commissioning with most of the Belle II subdetectors has been performed, and the readout upgrade is complete for the particle-identification detectors and the neutral kaon and muon detector in Belle II, which has been operating stably with the new system in the beam collision "physics runs." The results of the commissioning and the performance of the global DAQ operation will be reported.

关键词： Data acquisition (DAQ) data transfer field-programmable gate arrays high-energy physics instrumentation

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Towards Complete and Scalable Emulation of Quantum Algorithms on High-Performance Reconfigurable Computers

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IEEE TRANSACTIONS ON COMPUTERS 2023年第8期72卷 2350-2364页

作者： El-Araby, Esam Mahmud, Naveed Jeng, Mingyoung Joshua MacGillivray, Andrew Chaudhary, Manu Nobel, Md. Alvir Islam Ul Islam, S. M. Ishraq Levy, David Kneidel, Dylan Watson, Madeline R. Bauer, Jack G. Riachi, Andrew E. Univ Kansas Dept Elect Engn & Comp Sci Lawrence KS 66045 USA Florida Inst Technol Comp Engn & Sci Dept Melbourne FL 32901 USA

Contemporary quantum computers face many critical challenges that limit their usefulness for practical applications. A primary limiting factor is classical-to-quantum (C2Q) data encoding, which requires specific circuits for quantum state initialization. The required state initialization circuits are often complex and violate decoherence constraints, particularly for I/O intensive applications. Existing Noisy Intermediate-Scale Quantum (NISQ) devices are noise-sensitive and have low quantum bit (qubit) counts, thus limiting the applicability of C2Q circuits for encoding large and realistic datasets. This has made the study of complete and realistic circuits that include data encoding challenging and has also led to a heavy dependency on costly and resource-intensive simulations on classical platforms. In this work, we propose a cost-effective, classical-hardware-accelerated framework for realistic and complete emulation of quantum algorithms. The emulation framework incorporates components for the critical C2Q data encoding process, as well as architectures for quantum algorithms such as the quantum Haar transform (QHT). The framework is used to investigate optimizations for C2Q and QHT algorithms, and the corresponding optimized quantum circuits are presented. The framework is implemented on a High-Performance Reconfigurable Computer (HPRC) which emulates the proposed QHT circuits combined with proposed C2Q data encoding methods. For performance benchmarks, CPU-based emulations and simulations on a state-of-the-art quantum computing simulator are also carried out. Results show that the proposed hardware-accelerated emulation framework is more efficient in terms of speed and scalability compared to CPU-based emulation and simulation.

关键词： field-programmable gate arrays parallel processing quantum computing quantum encoding

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A generalized hardware architecture for real-time spiking neural networks

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NEURAL COMPUTING & APPLICATIONS 2023年第24期35卷 17821-17835页

作者： Valencia, Daniel Alimohammad, Amir San Diego State Univ Dept Elect & Comp Engn San Diego CA 92182 USA Univ Calif San Diego Dept Elect & Comp Engn La Jolla CA 92093 USA

This article presents an area- and power-efficient hardware architecture for the brain-implantable spiking neural networks (SNNs). The proposed generalized hardware architecture is parameterizable and reconfigurable such that the maximum supported number of neurons, the interconnection structure among neurons, and the resolution of the time step can be readily adjusted for realizing various SNN topologies. The designed SNN hardware architecture is capable of emulating moderately-sized SNNs with tens of thousands of neurons in real-time with varying degrees of parallelism, while reducing the resource utilization by 34% for similarly sized SNNs implemented on a single field-programmable gate array (FPGA). We evaluate the model using the MNIST digit recognition benchmark and show that the network can accurately classify handwritten digits with 89.8% accuracy. Compared to the other recently implemented SNN emulators based on FPGAs, the designed and implemented single-FPGA system is able to emulate moderately-sized SNNs instead of using a cluster of FPGAs or CPUs. The application-specific integrated circuit (ASIC) implementation of a moderately-sized SNN is estimated to occupy 3.6 mm(2) of silicon area. Post-layout synthesis and simulation results show that the ASIC will dissipate 3.6 mW of power from a 1.16 V supply while operating at 34.7 MHz in a standard 32-nm CMOS process.

关键词： Spiking-neural networks field-programmable gate arrays Application-specific integrated circuits Machine learning

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Fiber-on-Chip: Digital Emulation of Channel Impairments for Real-Time DSP Evaluation

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2023年第3期41卷 888-896页

作者： Borjeson, Erik Larsson-Edefors, Per Chalmers Univ Technol Dept Comp Sci & Engn S-41296 Gothenburg Sweden

We describe the Fiber-on-Chip (FoC) approach to verification of digital signal processing (DSP) circuits, where digital models of a fiber-optic communication system are implemented in the same hardware as the DSP under test. The approach can enable cost-effective long-term DSP evaluations without the need for complex optical-electronic testbeds with high-speed interfaces, shortening verification time and enabling deep bit-error rate evaluations. Our FoC system currently contains a digital model of a transmitter generating a pseudo-random bitstream and a digital model of a channel with additive white Gaussian noise, phase noise and polarization-mode dispersion. In addition, the FoC system contains digital features for real-time control of channel parameters, using low-speed communication interfaces, and for autonomous real-time analysis, which enable us to batch multiple unsupervised emulations on the same hardware. The FoC system can target both field-programmable gate arrays, for fast evaluation of fixed-point logic, and application-specific integrated circuits, for accurate power dissipation measurements.

关键词： field programmable gate arrays Hardware Optical transmitters Integrated circuit modeling Emulation Real-time systems Pipeline processing Application-specific integrated circuits channel models digital signal processing field-programmable gate arrays optical fiber communication very large-scale integration

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JACC-FPGA: A hardware accelerator for Jaccard similarity estimation using FPGAs in the cloud

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2023年 138卷 26-42页

作者： Soto, Javier E. Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Elect Engn Dept Concepcion Chile Univ Concepcion Comp Sci Dept Concepcion Chile Ctr Biotechnol & Bioengn CeBiB Santiago Chile

Genomic similarity is a key metric in genomics, used in important tasks such as genome clustering and metagenomic profiling. One commonly-used approach is to treat each genome as a set of k-mers and to compute the Jaccard coefficient between each genome pair. However, computing the Jaccard coefficient between genomes in a large dataset is a computationally-challenging task. In this paper, we present an algorithm and accelerator architecture that uses an FPGA-as-a-service paradigm to compute the Jaccard similarity between pairs of genomes in large datasets using sketches and hardware acceleration in the cloud. The algorithm can compute the similarity between all genome pairs in the dataset, or it can use a selection criterion to reduce the amount of computation when only genome pairs with a Jaccard coefficient above a user-supplied threshold are of interest. After building the sketches, our heterogeneous accelerator can compute more than 96 million Jaccard coefficients per second running on an AWS EC2 f1.2xlarge instance with a Xilinx XCVU9P FPGA, which is 58 times faster than a state-of-the art software implementation that exploits SIMD instructions and thread-level parallelism on a compute-optimized EC2 c5.9xlarge instance with 36 hardware threads. The accelerator also computes similarities 27 times faster than a straightforward GPU-accelerated implementation of the Jaccard coefficient using sketches, and 4 times faster than an optimized GPU implementation of our algorithm, both running on an EC2 g5.4xlarge instance tailored with an NVIDIA A10G GPU. Furthermore, using a Jaccard coefficient threshold of 0.8 reduces the execution time of similarity computation to approximately one third in the hardware-accelerated and parallel software implementations, compared to computing the complete similarity matrix.(C) 2022 Elsevier B.V. All rights reserved.

关键词： Hardware acceleration Cloud computing field-programmable gate arrays Streaming algorithms Sketches Genomics

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Nonlinear Behavioral Modeling and Real-Time Simulation of Electric Propulsion System for the High-Fidelity X-in-the-Loop Applications

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IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION 2023年第1期9卷 1708-1722页

作者： Bai, Hao Li, Qian Luo, Huan Huangfu, Yigeng Gao, Fei Northwestern Polytech Univ Sch Automat Xian 710072 Peoples R China Univ Bourgogne Franche Comte Franche Comte Elect Mech Thermal Sci & Opt Sci & Univ Technol Belft Montbeliard UTBM French Natl Ctr Sci Res CNRS F-90010 Belfort France Xian Univ Sci & Technol Sch Mat Sci & Engn Xian 710054 Peoples R China

The electric propulsion system (EPS) is an important enabling technology for electrified transportation. The short time-to-market of such a system relies on real-time simulation (RTS)-based efficient X-in-the-loop testing. To ensure high fidelity, the RTS should include the detailed behavior as much as possible while complying with the constraints of the model computing time. Therefore, a nonlinear behavioral real-time modeling approach is proposed for the EPS in this article, including the adaptive curve-fitting (ACF)-based device-level power electronics model and the nonlinear flux-linkage-based spatial harmonic (FLSH) PMSM model. The real-time models are designed and implemented on the NI FLEXRIO FPGA module. Ultralow RTS latencies are realized for the ACF power converter model and the FLSH PMSM model, which are 25 and 160 ns, respectively. The simulation accuracies are consistent with the off-line simulation tools. Moreover, the ACF model and the FLSH model are used in the RTS of a fuel cell electric vehicle (FCEV) EPS together with the generic fuel cell model, the battery model, and the vehicle dynamic motion model. The RTS results prove that the proposed EPS real-time model is an excellent candidate for RTS applications.

关键词： Computational modeling Integrated circuit modeling Transient analysis Real-time systems Switches Adaptation models Biological system modeling field-programmable gate arrays modeling power electronics real-time system simulation

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